Patents Examined by John Follensbee
  • Patent number: 6049828
    Abstract: A network management system includes a user interface, a virtual network and a device communication manager. The virtual network includes models which represent network entities and model relations which represent relations between network entities. Each model includes network data relating to a corresponding network entity and one or more inference handlers for processing the network data to provide user information. The system can poll or communicate with certain network entities and can infer the status of network connectors and other network entities for which polling is impossible or impractical. The system performs a fault isolation technique wherein the fault status of a network device is suppressed when it is determined that the device is not defective. User displays include hierarchical location views and topological views of the network configuration.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: April 11, 2000
    Assignee: Cabletron Systems, Inc.
    Inventors: Roger H. Dev, Mark H. Nelson
  • Patent number: 6047304
    Abstract: A method and apparatus for processing network packets is disclosed. A Single Instruction Multiple Data (SIMD) architecture processor is disclosed. The SIMD processor includes several instructions designed specifically for the task of network packet processing. For example, SIMD add instructions for performing one's complement additions are included to quickly calculate Internet checksums. Furthermore, the SIMD processor includes several instructions for performing lane arithmetic.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: April 4, 2000
    Assignee: Nortel Networks Corporation
    Inventors: Geoff Ladwig, Edward S. Harriman
  • Patent number: 6044452
    Abstract: A method of processing comprising first connecting a desk top computer to a portable computer; and then symmetrically processing.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: March 28, 2000
    Assignee: Micron Electronics, Inc.
    Inventors: Kenneth Birch, Paul Petersen, Todd Farrell
  • Patent number: 5999991
    Abstract: The present invention relates to a computer system and more particularly to a computer system which allows option controller cards for various input/output (I/O) devices to be added on the motherboard at minimum cost.
    Type: Grant
    Filed: August 5, 1997
    Date of Patent: December 7, 1999
    Assignee: Packard Bell NEC
    Inventors: Jimmy Dean Smith, Mark D. Nicol, Brian K. Straup, Terence Paul O'Brien, Mark Layne Herman
  • Patent number: 5822605
    Abstract: In a parallel processor system comprising a plurality of processor elements constituting a network, a source processor element wishing to broadcast data to a plurality of destination processor elements sends a broadcast request message containing the target data to a broadcast exchanger. The broadcast exchanger converts the received message into a broadcast message and sends it over the network to the destinations. A plurality of broadcast request messages, if transmitted parallelly to the broadcast exchanger, are serialized thereby so that only one broadcast message will be transmitted at a time over the network. This prevents deadlock from occurring between different broadcast messages. The routes for transmitting broadcast request messages and those for transmitting broadcast messages are arranged so as not to overlap with one another. This suppresses deadlock between any broadcast request message and broadcast message. The broadcast exchanger is replaced alternatively with one of the partial networks.
    Type: Grant
    Filed: March 22, 1995
    Date of Patent: October 13, 1998
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Tatsuo Higuchi, Tadaaki Isobe, Junji Nakagoshi, Shigeo Takeuchi, Tatsuru Toba, Yoshiko Yasuda, Teruo Tanaka, Takayuki Nakagawa, Yuji Saeki
  • Patent number: 5819023
    Abstract: The integrated circuit comprises a central processing unit, a program memory containing a program of instructions connected to the central processing unit by an address bus, a data bus and lines giving control signals for read and write access to this memory, the instructions being carried out by the central processing unit, and at least one data memory connected to the central processing unit by an address bus, a data bus and lines giving control signals for read and write access to this memory. The circuit comprises breaking means enabling the defining of a combination of conditions pertaining to the values present on two of the buses of the memories and to the values of the control signals for access to at least one of these memories, and halting the performance of the instructions if these conditions are verified. The disclosed device is especially valuable for testing an application program of the integrated circuit.
    Type: Grant
    Filed: May 18, 1995
    Date of Patent: October 6, 1998
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Stephan Klingler