Abstract: An asynchronous arbiter circuit processes multiple different address signals that request access to the same memory location during the same memroy cycle. The circuit employs two sets of latches. The circuit recognizes access request signals and refresh request signals. For each type of request signal recognized, an associated first latch stores the value of the request signal received, and outputs a first latch output signal. An associated second latch receives the first output latch signal and translates that into a logic state that is long enough to ascertain whether additional request signals have been inputted into the circuit during the memory cycle. A delay element delays one of the request signals received prior to the signals being inputted into the cycle request logic element. The time period of the delay is determined based upon priority accorded to the particular signals.

Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Abstract: On-line documentation for an application program resides in a number of help modules. A display file for the application program specifies command panels to be displayed. The command panel definition includes a mapping of screen areas to help modules as well as a designation of an index-sensitive search table. A user may access the on-line documentation either by pressing a function key for context-sensitive help (which displays the help module mapped to current cursor position) or by entering search words in an entry area for index-sensitive help. Index-sensitive help searches a table of synonyms, roots and topics which map to help modules, and lists the modules associated with the search word ordered by number of hits. Each command panel definition may specify a separate index-sensitive search table, permitting customization of the search to the application. The user then selects one or more of the listed modules for display.

Abstract: Tasks may be planned for execution on a single processor or are split up by the designer for execution among a plurality of signal processors. The tasks are modeled using a design aid called a precedence graph, from which a dependency table and a prerequisite table are established for reference within each processor. During execution, at the completion of a given task, an end of task interrupt is provided from any processor which has completed a task to any and all other processors including itself in which completion of that task is a prerequisite for commencement of any dependent tasks. The relevant updated data may be transferred by the processor either before or after signalling task completion to the processors needing the updated data prior to commencing execution of the dependent tasks. Coherency may be ensured, however, by sending the data before the interrupt.

Abstract: A task communicator for each node in a multiple node processing system having a data memory storing data received from a voter interface which is used for the execution of tasks by an associated applications processor, a next task register storing the identification code of the next task to be executed by the applications processor received from a scheduler through a scheduler interface. An input handler passes the identification code of the next task and the data required for the execution of that task to an input FIFO register interfacing the applications processor. An output FIFO register temporarily stores the data generated by the applications processor and an output handler generates inter-node messages containing data stored in the output FIFO and passes these inter-node messages to a transmitter through a transmitter interface for transmission to all of the other nodes in the processing system.

Abstract: A microprocessor control system for use in an asynchronous data communication system and comprising a receive microprocessor and a transmit microprocessor along with a paged memory for storing channel line tables. Separate receive and transmit channel number registers control access to the paged memory. Control means is provided preferably in the form of a programmable memory for controlling the sequenching of channel numbers whereby one microprocessor is adapted to access channels in an incrementing manner while the other accesses in decrementing manner. When one microprocessor gains access to a specific line table excludes the other microprocessor from accessing that line table until the first microprocessor suspends off of that line table.

Abstract: An access control or arbitrator for a shared resource, such as a time-slotted bus, groups requests according to priorities of the requests. The time slots are grouped into sets, each set having a number of successive time slots equal to the number of sources supplying access requests having a highest priority. In a highest priority group, each source supplying a highest priority access request is guaranteed access in respective ones of said time slots in each set of time slots. When any time slot is not being used by a high priority request, low priority requests then have access to the unused time slot. Lower priority groups of access requests are handled in accordance with a different algorithm, such as a round robin priority algorithm.

Abstract: A parallel data processing system comprises a control data processor and a plurality of processing planes, each of the planes comprising a plurality of data processing cells. Each of the cells within a plane is communicatively coupled to adjacent, coplanarly disposed cells and, in addition, is communicatively coupled to a corrresponding cell disposed in an overlying processing plane and to a corresponding cell disposed in an underlying processing plane. The control data processor is coupled to each of the cells within a given plane in a manner which provides for simultaneous communication with each of the cells within the plane. Each of the cells within a plane is provided with an output status signal operable for being combined with the output status signals from other cells within the plane to provide an input signal to the control data processor.

Abstract: A prescribed menu item on a menu table (108b) is picked to designate a method of defining a figure element, and a predefined figure element displayed on a display screen (106) is picked. A processor (102) defines a new figure element using the picked figure element definition method and the picked figure element, and defines a part profile using figure elements picked in the order of tool motion when the defining of all figure elements is completed. In this case, the processor expresses, in a first format based upon an automatic programming language, figure elements and the part profile as defined, and stores the figure elements and part profile in a storage ares (103b). Using a second format for the figure elements, each point is expressed as the coordinate values thereof, each straight line expressed as the coordinate values of two points, and each circle expressed as the coordinates of the center of the circle and the radius of the circular arc, are stored in a storage area 103c.

Abstract: A method for making files compatible between different computers having different binary structures while using the same operating system by keeping all files in a standardized canonical order when they move to or from external data storage or communication means. The method includes converting all binary data accessed from a file or communications channel from the canonical order to the natural order of the host computer before using the binary data in the host computer and converting all binary data which is to be sent to a file or communications channel from the natural order of the host computer to the canonical order before sending the binary data.

Abstract: The disclosure relates to sequential performance of a cached data storage subsystem with a minimal control signal processing. Sequential access is first detected by monitoring and examining the quantity of data accessed per unit of data storage (track) across a set of contiguously addressable tracks. Since the occupancy of the data in the cache is usually time limited, this examination provides an indication of the rate of sequential processing for a data set, i.e., a data set is being processed usually in contiguously addressable data storage units of a data storage system. Based upon the examination of a group of the tracks in a cache, the amount of data to be promoted to the cache from a backing store in anticipation of future host processor references is optimized. A promotion factor is calculated by combining the access extents monitored in the individual data storage areas and is expressed in a number of tracks units to be promoted.

Abstract: A data processing apparatus having an input device for entering data, and a timer connected to the input device for measuring a predetermined time duration during which a data entry operation through the input device is interrupted. The apparatus is provided with a display, buzzer or any visual, audio or optical device for providing information associated with the data entry operation interrupted, when the timer has measured the predetermined time duration. The associated information may be a candidate word or words to be substituted for a word in the process of entry into an electronic typewriter or a word processor. The associated information may also be information such as addresses or telephone numbers of persons or companies whose data have been entered prior to the data input interruption. Further, the associated information may be a message prompting the operator to enter a specific kind of data, or information indicative of an operation that should be performed after the interruption of data entry.

Abstract: The present invention relates to a method and apparatus for preparing a series of daily menus that include foods having preselected characteristics. The menus are prepared from a list containing numerous food items, the caloric content of each item, which food group each item resides, and the applicability of each item for a particular meal. The daily menus are created from the items in the list in a manner such that each meal in each menu only includes items which are applicable to that meal, each meal has items from each of a preselected number of food groups, and each meal has a predetermined caloric content. After the menus are formed, selected items in the menus can be replaced, with each replacement item being applicable for the particular meal, being in the same food group, and having the same caloric content as the item that is replaced.

Abstract: In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.

Abstract: A multi-processor system has a main memory shared by a plurality of processors, two operating systems, a local supervisor for executing processing in a local area and a global supervisor for executing processing which requires access to a common area. When the local supervisor needs processing which requires access to an area other than the local area, it requests that execution of the processing be effected by the global supervisor. Thus, the local supervisor executes the processing only in the local area. More than one processor will do not simultaneously execute processing in one local area.

Abstract: A pipelined processor to improve the efficiency of conventional pipelined instruction processing including a two stage instruction decoder which converts sets of similar conventional instructions having the general formats: "MOV: A R1 R2" and "MOV: B R1 R2" where the letter fields A,B etc. indicate the direction of data transfer between the registers, R1, R2; into a single format instruction which can be processed by one microprogram. The first stage decoder processes one instruction intact and generates an intermediate code for the remaining format instruction. The second stage decoder utilizes the intermediate code to specify the direction of transfer by reversing the sequence of register numbers in the instruction not processed intact by the first stage. The resulting transfer instructions have the same format and thus require one, rather than two, microprograms for execution, making the pipelined processor more efficient.

Abstract: A tightly coupled data processing system having high performance characteristics, including at least one general purpose host processor coupled to host processor ports of a High Performance Storage Unit, and a Scientific Processor directly coupled to scientific processor ports of the High Performance Storage Unit is described. The Scientific Processor is under task assignment control of the host processor and shares the same memory space as the host processor, and thereby provides the tight coupling without need of dedicated memory or caching. Provision is also made for the Scientific Processor to share the virtual address space of the host processor. A tightly coupled system is also disclosed wherein a plurality of general purpose host processors are each coupled to one or more High Performance Storage Units, and a Multiple Unit Adapter is utilized to couple an associated Scientific Processor to all of the High Performance Storage Units.

Abstract: A typical peripheral system includes a control path and a data path along with a peripheral controller that processes different type of instructions for control and data paths. Since control and data paths are not independent of each other, it is necessary to either combine these two types of instructions in a single instruction or execute these two types of instructions in a prescribed manner so that a control path instruction can be executed while a data path instruction is being executed. The data path instructions (which may also be called event-count instructions) includes serialization and deserialization of data and other information such as ECC, and typically have lengths of events, or fields, typically in words and bytes associated with them. Control instructions (which may also be referred to as nonevent-count instructions) include setting of tag patterns, branching or jumping or typically have no fields of data associated with them.

Abstract: A method and apparatus for controlling access to data blocks stored by addresses in a memory and concurrently accessible by a plurality of transactions is provided. The method includes the steps of receiving an address of a data block to be accessed by a first transaction, deriving from the address an access table entry corresponding to the data block where the entry includes lock data that governs access to the data block, and providing the access if permitted by the lock data, or providing the access, if not permitted by the lock data, and recording the occurrence of the access in the lock data.

Abstract: A mounting arrangement for diskette drives in a cabinet of electronic apparatus includes an assembly for accommodating two diskette drives or one diskette drive and a removable diskette storage unit mounted in the space reserved for the second diskette drive. The assembly is adapted for quick and easy mount/dismount in and from the cabinet and the removable storage unit provides a convenient storage space for a number of often used diskettes in a space which is typically wasted until installation of a second diskette drive unit is required.