Abstract: A massively parallel processor apparatus having an instruction set architecture for each of the N.sup.2 the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of PEs that contain instruction and data storage units, receive instructions and data, and execute instructions. The N.sup.2 structure should contain "N" communicating ALU trees, "N" programmable root tree processor units, and an arrangement for communicating both instructions, data, and the root tree processor outputs back to the input processing elements by means of the communicating ALU trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 PEs, identified as PE.sub.column,row, in a N root tree processor system, placed in the form of a N by N processor array that has been folded along the diagonal and made up of diagonal cells and general cells. The Diagonal-Cells are comprised of a single processing element identified as PE.sub.

Abstract: A receive buffer management system associates a virtual buffer pool with each node communicating with a receiver and creates an actual buffer pool for use by all nodes, with a "low-water-mark" indicating buffers are running out and a "high-water-mark" indicating enough buffers are available. Each time a buffer is taken a count is added to the virtual pool for that sending node and each time a buffer is returned to the actual pool, the counter for the sending node's virtual pool is decremented. Each virtual pool has a quota. Buffers are allocated until the number of buffers in the actual buffer pool drops below the low-water-mark. Then packets from a node above its quota will be discarded and those buffers will be immediately returned to the actual pool. Packets will be discarded for all over-quota nodes until those nodes drop below their quota or the actual pool reaches the high-water-mark. Alternatively, a sliding window acknowledgement replaces the virtual pool and counter.

Abstract: A file access scheme in a distributed data processing system for executing an access to a file in response to a file server to effect a data processing includes a device for executing an input/output processing such that each processing module unit operates as a subroutine of a data processing unit and executes input/output processing to the file controlled by itself and a device for executing data transfer processing such that the processing module unit operates as a subroutine of the data processing unit and implements a data transfer processing between the processing module unit and the file server of other processing modules.

Abstract: A system for maintaining the integrity of data stored in a branch prediction mechanism such as a branch target buffer (BTB). Upon encountering a branch instruction, a stream of target instructions is prefetched from cache memory even though the target instruction stream is provided from the BTB. The target instruction stream prefetched from cache is then compared with the predicted target stream selected from the BTB. Upon encountering a mismatch, the predicted instruction stream is canceled and the instructions from cache are utilized. Additionally, predicted branch target addresses are stored in a BTB, similar to a branch history table, and circuitry is provided for comparing the predicted target address with an actual target address during processing of the branch instruction. Again upon encountering a mismatch, instruction from cache as addressed by the actual target address are utilized and predicted instructions are canceled.

Abstract: A data processor having a string operation instruction and a bit map operation instruction, and comprises a bus interface unit 157 which inputs/outputs data by the burst transfer function, and an integer operation unit 155 building-in a main ALU and a sub-ALU, wherein data is repeatedly transferred to/from an external memory via a data bus 102 in unit greater than a width of the data bus 102. Further, is can be accessed in a high speed by the block transfer in the burst mode to efficiently execute the above instructions, therefore the data string and bit map data can be executed quickly even when a low-cost slow memory system is connected thereto.

Abstract: A sorting apparatus is composed of sort processors connected in a pipeline fashion. Each sort processor 106 merge sorts data from the preceding sort processor and then outputs the merge sort result to the succeeding sort processor. The sort processor includes sort core portions and a front end internal storage and a back end internal storage for the respective sort core portions. Outside the sort processors, there are added external memories for the respective sort core portions. The front and back end internal storages and the external memories constitute a local memory. The sort core portions use, when a faulty area is found in the local memory, part of the front end and back end internal storages as an alternative memory.

Abstract: Distributed processing systems having a host processor and at least one object oriented processor are disclosed. An object oriented processor according to the invention has a communications interface, an intelligent message handler, and a task-specific functionality. The communications interface is coupled to a host processor via a message based communications link. A high level command language is provided which is easily implemented in a host processor program. The command language includes subsets of commands which are understood by different object oriented processors having different functionality. According to one embodiment, the object oriented processor includes support for a broad array of input and output devices. The command language includes high level commands for initializing, reading from and/or writing to the peripherals supported by the object oriented processor.

Abstract: A trigger is armed to a predetermined detection point (DP) of a basic call state model controlled for each call by a switching system so that a service control point (SCP) can be unconditionally activated. The SCP stores service control information for each time band in such a manner as to correspond to each user. When a first control signal is received from the switching system, the DP which is determined by the service control information is notified to the switching system and the switching system arms the trigger to this DP. When the state of the call shifts to a specific DP to which the trigger is armed because a called party is busy or does not answer, for example, the switching system sends a second control signal to the SCP, and the SCP notifies a terminating terminal equipment determined by the service control information in response to the second control signal.

Abstract: A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for providing communication from the integrated circuits to a board bus. One multi-chip package contains additional bus interface circuitry for providing communication from the board bus to a backplane bus.

Abstract: A method for managing communication between a client process and a server process in a distributed computing environment, the client process residing on a host computer that is connected to a physical network having a transport layer and a network layer. The method begins when the client process makes a remote procedure call by detecting whether a server process identified by the remote procedure call is located on the host computer. If so, a binding handle vector is returned to the client process. The protocol sequence in the binding handle is mapped to a second protocol sequence that establishes an interprocess communication path between the client and server processes instead of a path through the transport and network layers of the physical network. The remote procedure call is then executed, preferably by using a send and receive messaging facility of the host computer operating system.

Abstract: A massively parallel processor apparatus having an instruction set architecture for each of the N.sup.2 the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of PEs that contain instruction and data storage units, receive instructions and data, and execute instructions. The N.sup.2 structure should contain "N" communicating ALU trees, "N" programmable root tree processor units, and an arrangement for communicating both instructions, data, and the root tree processor outputs back to the input processing elements by means of the communicating ALU trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 PEs, identified as PE.sub.column,row, in a N root tree processor system, placed in the form of a N by N processor array that has been folded along the diagonal and made up of diagonal cells and general cells. The Diagonal-Cells are comprised of a single processing element identified as PE.sub.

Abstract: A data processing system is programmed to display an annotatable bit map image of a text document, a spreadsheet and the like. Annotations are superimposed on a displayed, annotatable image, under control of an annotation program, in response to an input device, such as a mouse, keyboard or stylus (or pen) and electrical writing tablet. An annotatable bit map image and, any annotation superimposed thereon during an annotation session, are reduced in size to a miniature size stamp image in response to a selection input received by the processor from an input device. The stamp image is of a size which is recognizable to a user due to its resemblance to the large size annotatable image of a document and annotations thereto, if any. In turn, an annotatable bit map image, whether annotated or not, is expandable to the larger annotatable image in response to selection inputs supplied to the programmed processor from an input device.

Abstract: A Multi-Chip-Module (MCM) microcircuit comprises a substrate, a plurality of integrated circuit processors mounted on the substrate, and an Advanced Programmable Interrupt Controller (APIC) system for distributing interrupts to the processors. The APIC system comprises a plurality of local units for prioritizing and passing interrupts to the processors respectively, and an Input/Output (I/O) unit for feeding interrupts to processors to which the interrupts are addressed. Electrical conductor patterns are formed on and between dielectric layers of the substrate for interconnecting the processors, the local units and the I/O unit.

Abstract: An information processing apparatus includes a main case body having installed thereon a key group at a key installation region thereof, a track ball and a selection switch (including a right switch and a left switch) are separately provided, respectively, at a right side region and a left side region of an operator side of the key installation region. The track ball, the right switch and the left switch are provided in such a manner so as an installation region of a wiring substrate. The track ball, the right switch, and the left switch can be easily operated under a key operation feeling by using both hands in a manner similar to operation of the key group. By the foregoing configuration, an increase in an occupied area of a keyboard can be reduced, and increase in a thickness of the keyboard can be restrained, thereby allowing the information processing apparatus to have superior operation characteristics, insofar as its pointing device is concerned.

Abstract: Proposed is a device which makes it possible to switch several processors from an instantaneous status to a follow-on status. The device is intended in particular for memory-programmable control units, referred to as memory-programmable status control units.

Abstract: The present invention relates to a fault tolerant system for providing power to a multiple central processing unit computer system. Three DC-DC converters, each sized for providing power to one central processing unit, furnish power to two central processing units through two power planes. Each DC-DC converter has an output voltage level selectable through a voltage identification signal. If the voltage identification signals of the converters match, identification logic couples the power planes together. If only one converter is available to power the two central processing units, a stopclock logic circuit alternatively places the central processing units in known stopclock modes. Thus, the single converter only has to fully power one central processing unit at any one time.

Abstract: Peripherals connected to an external bus is connected to a power source section through switching units, and a buffer circuit connected to an internal bus and the external bus is consisted of a separating unit. An internal memory and power consumption reducing unit for controlling the switching units and the separating unit are provided in a processing unit. After program or data is transferred and stored from external memories to the internal memory through the external bus, the power consumption reducing unit keeps a low power consumption of the external peripherals by controlling the switching units, and the internal bus of the processing unit is disconnected from the external bus by controlling the separating unit. Thus, the power consumption of overall system will be restrained from increasing.

Abstract: A data transmission method is provided for a multi-computer system which has a plurality of computers mutually connected via a transmission line. The plurality of computers are divided into groups, with an address assigned to each group. Transmission data of a sending computer is provided with a location where the address is assigned and a location where a content code indicating the data content is assigned. The sending computer transmits the data with either the address or content code assigned, and the computers other than the sending computer decide whether or not to receive the data according to either the address or the content code.

Abstract: In accordance with the present invention, a microprocessor controlled device is provided which appears to a user to be a programmable logic device. Signals are taken from and placed on external pins in the same manner as would be done with a prior art programmable logic device. However, internal hardware which would be provided in a programmable logic device for performing the logic function is replaced by a microprocessor with associated memory. The microprocessor is programmable to read input signals from input pins, perform calculations related to the desired logic, and place signals onto output pins. Thus the function of the microprocessor controlled device as it appears from observing signals on external pins is the same as that of a prior art FPGA or other logic device.

Abstract: The system for supporting input or reference of a data value or a structure value which is a component of a PDU (Protocol Data Unit). The abstract syntax of PDU is defined in accordance with ISO8824 (international standard ASN.1 (Abstract Syntax Notation One) specification) and the PDU is encoded/decoded conforming to ASN.1 basic encoding rules in ISO8825. The data value and the structure value are described in the form of substitute statement of the abstract syntax identifier.