Patents Examined by John I. Chavis
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Patent number: 5696974Abstract: Methods and related apparatus, for use in programming language systems, are set forth which support compile-time type checking for overloaded functions in an environment supporting subtypes with multiple inheritance. At both compile and runtime, the invention considers the type of all actual arguments of a function to select a proper function instance to execute. Furthermore, the methods contemplated by the invention identify at compile time the set of function instances which might be invoked due to subtype substitutions for the actual arguments. Since type errors on function invocations or variable assignments are usually indicative of a programming error, program reliability can be improved and faults that would otherwise result in runtime errors can be corrected through the use of the invention prior to program deployment.Type: GrantFiled: November 7, 1995Date of Patent: December 9, 1997Assignee: International Business Machines CorporationInventors: Rakesh Agrawal, Linda Gail De Michiel, Bruce Gilbert Lindsay
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Patent number: 5680619Abstract: An application development system, optimized for authoring multimedia titles, enables its users to create selectively reusable object containers merely by defining links among instantiated objects. Employing a technique known as Hierarchical Encapsulation, the system automatically isolates the external dependencies of the object containers created by its users, thereby facilitating reusability of object containers and the objects they contain in other container environments. Authors create two basic types of objects: Elements, which are the key actors within an application, and Modifiers, which modify an Element's characteristics. The object containers (Elements and Behaviors--i.e., Modifier containers) created by authors spawn hierarchies of objects, including the Structural Hierarchy of Elements within Elements, and the Behavioral Hierarchy, within an Element, of Behaviors (and other Modifiers) within Behaviors.Type: GrantFiled: April 3, 1995Date of Patent: October 21, 1997Assignee: mFactory, Inc.Inventors: Norman K. Gudmundson, R. Hamish Forsythe, Wayne A. Lee
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Patent number: 5671419Abstract: A computer implemented method performs flow-sensitive interprocedural data flow analysis without iteration for a class of interprocedural problems. The accuracy of the solution can approach the iterative result without the compile time cost. For interprocedural constant propagation (ICP), this method is more effective than existing methods and costs about the same compilation time. For flow-sensitive ICP over a program call graph (PCG), the method supports recursion while only performing one flow-sensitive analysis of each routine. If the PCG has cycles, a flow-insensitive solution is precomputed for constant propagation. During the flow-sensitive computation, the flow-insensitive result is used for a back edge. This permits a flow-sensitive solution to be obtained in one forward traversal of the PCG. This method can also be used to compute returned constants with one reverse traversal of the PCG.Type: GrantFiled: June 15, 1995Date of Patent: September 23, 1997Assignee: International Business Machines CorporationInventors: Paul Robert Carini, Michael George Burke, Michael James Hind
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Patent number: 5659747Abstract: A multiple-level undo/redo mechanism is provided in an operating system and is available to application programs run on the operating system. The operating system provides a mechanism for keeping a log of user commands and providing a cursor to a position within the log. Each command may be encapsulated into an object that supports an interface for performing undo/redo operations. Similarly, the log may be encapsulated into an object that supports operations that facilitate a multiple-level undo/redo. A user may perform a single undo/redo operation, multiple successive undo/redo operations or complete undo/redo operations.Type: GrantFiled: April 22, 1993Date of Patent: August 19, 1997Assignee: Microsoft CorporationInventor: Satoshi Nakajima
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Patent number: 5630057Abstract: A computer architectural and apparatus system for preventing software copying or alteration, and providing enhanced computational capabilities, physical information security, and physical environment protection is disclosed. The system comprises an Independent Computer Module (ICM), and an Interface Unit. The ICM comprises a CPU, a RAM, a ROM, a memory switching means, a communications port, and a connectorless interface contained within a sealed cartridge. The Interface Unit comprises a receptacle for receiving the ICM, which contains a matching connectorless interface, and wiring to a host computer's port and power. The connectorless interface uses directional electro-magnetic emitters and sensors to prevent signal leakage. The memory switching means turns off the entire secure memory, enabling non-secure programs to be run from another section of RAM. Reactivation of secure memory by a non-secure program causes program control to be transferred to a fixed address within the secure program.Type: GrantFiled: July 1, 1996Date of Patent: May 13, 1997Assignee: Progressive Technology Inc.Inventor: John N. Hait
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Patent number: 5590329Abstract: Disclosed is a software generation system (SGS) based memory error detection system which may be utilized to detect various memory access errors, such as array dimension violations, dereferencing of invalid pointers, accessing freed memory, reading uninitialized memory, and automated detection of memory leaks. Error checking commands and additional information are inserted into a parse tree associated with a source code file being tested at read-time which serve to initiate and facilitate run-time error detection processes. Wrapper functions may be provided for initiating error checking processes for associated library functions. A pointer check table maintains pointer information, including valid range information, for each pointer that is utilized to monitor the use and modification of the respective pointers.Type: GrantFiled: February 4, 1994Date of Patent: December 31, 1996Assignee: Lucent Technologies Inc.Inventors: James E. Goodnow, II, Thaddeus J. Kowalski, James R. Rowland
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Patent number: 5581746Abstract: A synchronous LSI memory device, comprises memory cell array sections (BK1, BK2) each having a plurality of memory cells; a timing generating section (CLOCK MASKED SECT) for generating a first basic signal (CPOR) synchronous with a clock signal (CLK) and masked according to the status of a control signal (CKE); a signal generating section (SERIAL SYS CONTROL) for generating a second signal (CP) in synchronism with the first basic signal (CPOR) and stopping generating the second signal after a predetermined number of accesses or in response to a stop signal (MRRST, MWSTP, LADA, BSTP); and a control section (SHIFT REGISTER) for controlling the cell array sections (BK1, BK2) on the basis of outputs of the timing signal generating section and the signal generating section.Type: GrantFiled: December 28, 1993Date of Patent: December 3, 1996Assignee: Kabushiki Kaisha ToshibaInventor: Yuji Watanabe
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Patent number: 5546581Abstract: A method is disclosed for integrating a plurality of discrete subprograms with a main program. The method enables the main program to integrate any discrete subprogram stored in its directory with the main program. The method includes the step of identifying each discrete subprogram stored in the directory of the main program and creating a cross reference array to enable the main program to access the plurality of subprograms. In addition to creating the cross reference array, an event reference list of the main program is updated, enabling commands of the subprogram to be given key and menu assignments, thereby further integrating the subprogram with the main program. Similarly, the subprogram can be removed from the main program simply by deleting the subprogram from the directory of the main program.Type: GrantFiled: March 8, 1994Date of Patent: August 13, 1996Assignee: Microsoft CorporationInventors: David R. R. McKinnis, David L. Luebbert, Eric R. Berman, Thomas W. Saxton, Daniel H. Padwa
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Patent number: 5513355Abstract: A control system for a switching system that is optimally flexible. In order to achieve this goal, the operating system of the control system contains a services management system that makes it possible for service processes to utilize other service processes for the implementation of their services without knowing their location in the control system.Type: GrantFiled: February 5, 1993Date of Patent: April 30, 1996Assignee: Siemens AktiengesellschaftInventors: Carl-Heinz Doellinger, Martin Wollensak
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Patent number: 5481720Abstract: In a distributed data processing system, the authentication of a process at one node for the use of a service at another node is performed in a facility that is separate from the requestor and service process. The separate facility is also replaceable, thereby allowing different authentication policies to be implemented within the distributed data processing system. The requesting process and the service process merely pass the authentication information between themselves without attempting to interpret the work of the separate authentication facility. In addition to authenticating the requestor to the service, the service is also authenticated to the requestor.Type: GrantFiled: September 14, 1994Date of Patent: January 2, 1996Assignee: International Business Machines CorporationInventors: Larry K. Loucks, Todd A. Smith
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Patent number: 5469561Abstract: An apparatus and method for controlling the bus cycle running time of a data processing apparatus. The apparatus includes a CPU and at least one device such as a memory device, input/output device and the like which receives data from the C. A clock signal supplied to the CPU is varied based on the bus cycle or address within the device which is identified by the CPU for processing of the data. Alternatively, the frequency of the clock signal is varied based on ambient temperature and line voltage conditions. Accordingly, processing speed of the CPU can be varied to accommodate high speed memory devices and slower speed input/output devices.Type: GrantFiled: December 22, 1992Date of Patent: November 21, 1995Assignee: Seiko Epson CorporationInventor: Koji Takeda
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Patent number: 5454110Abstract: This invention describes a set of methods and techniques that together address the deficiencies of the basic input/output system (BIOS) and the advanced basic input/output system (ABIOS) in the context of a pen-based portable computer while retaining much of its strengths in terms of providing an insulating layer between the hardware and the operating system such that the same operating system code body will execute in a variety of hardware platforms. In particular, the following deficiencies have been addressed. (a) A dual boot capability allowing the user to select, through a set-up procedure, either a conventional (DOS-style) booting procedure or a Penpoint-style booting procedure. (b) The capability to mast certain device characteristics from the operating system, defined as a callback mechanism. (c) A method for collecting and maintaining device state information of a device that could be disconnected or reconnected during the operating of the computer.Type: GrantFiled: August 26, 1994Date of Patent: September 26, 1995Assignee: International Business Machines CorporationInventors: Krishnamurthl Kannan, David P. Lybrand, Frank P. Novak