Patents Examined by John Lindlof
  • Patent number: 10078521
    Abstract: Techniques are described herein for storing and processing codes included in dictionary-encoded data. In an embodiment, for each respective code of a plurality of codes in the dictionary-encoded data: a plurality of bits from a first portion of the respective code is contiguously stored. One or more bits from a second portion of the respective code is stored in one or more slices. Each respective slice of the one or more slices stores a bit from the one or more bits with a corresponding bit position in the respective code. In another embodiment, a bit-vector is generated based on at least one slice by loading each respective bit of the plurality of bits into different respective partitions in a register at a bit position corresponding to the at least one slice. A plurality of codes may be reconstructed by combining the bit-vector with one or more other bit-vectors.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: September 18, 2018
    Assignee: Oracle International Corporation
    Inventors: Shasank Kisan Chavan, Phumpong Watanaprakornkul, Amit Ganesh, Vineet Marwah
  • Patent number: 10055237
    Abstract: In one general aspect, a system includes an abstract machine instruction stream, a virtual machine coprocessor configured to receive an instruction from the abstract machine instruction stream and to generate one or more native machine instructions in response to the received instruction, and a processor coupled to the virtual machine coprocessor and operable to execute the native machine instructions generated by the virtual machine coprocessor. The virtual machine coprocessor is operable to generate one or more native machine instructions to explicitly control the virtual machine coprocessor.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: August 21, 2018
    Assignee: ARM Finance Overseas Limited
    Inventor: Kevin D. Kissell
  • Patent number: 10055229
    Abstract: In a pipeline where first and second instruction slots process first and second instructions in parallel and a duplicated processing resource is provided at both first and second pipeline stages, a second instruction in the second instruction slot requiring the duplicated processing resource is controlled to use the duplicated processing resource at the first pipeline stage when a first number of cycles by which the instruction in the first instruction slot is to be stalled is greater than or equal to a second number of cycles by which the second instruction would be stalled to allow its operand to be available in time for the first pipeline stage.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: August 21, 2018
    Assignee: ARM Limited
    Inventor: Spyros Lyberis
  • Patent number: 10055225
    Abstract: A processor fetches a multi-register scatter instruction that includes a source operand and a destination operand. The source operand specifies a source vector register that includes multiple source data elements. The destination operand identifies multiple destination data elements that each specify a destination vector register and an index into that destination vector register. The instruction is decoded and executed, causing, for each of those identified destination data elements, the one of the source data elements that is in a position in the source vector register that corresponds with a position of that destination data element to be stored in the destination vector register at the index specified by that destination data element.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: August 21, 2018
    Assignee: Intel Corporation
    Inventor: Ashish Jha
  • Patent number: 10042647
    Abstract: Managing a divided load reorder queue including storing load instruction data for a load instruction in an expanded LRQ entry in the LRQ; launching the load instruction from the expanded LRQ entry; determining that the load instruction is in a finished state; moving a subset of the load instruction data from the expanded LRQ entry to a compact LRQ entry in the LRQ, wherein the compact LRQ entry is smaller than the expanded LRQ entry; and removing the load instruction data from the expanded LRQ entry.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Richard J. Eickemeyer, David A. Hrusecky, Elizabeth A. McGlone, Brian W. Thompto, Albert J. Van Norstrand, Jr.
  • Patent number: 10031751
    Abstract: A processing device includes an instruction control unit outputting an instruction fetch request; a primary cache having a request port for the instruction fetch request and a cache processing unit that outputs instruction data for the instruction fetch request; and a secondary cache returning the instruction data to the primary cache. The request port has a primary port provided in common to threads and storing information on the instruction fetch requests of the threads, secondary ports provided for each threads, and each storing entry numbers of the primary port, and a request determination unit determining, from among the entered instruction fetch requests, an instruction fetch request to be input to the primary cache, with priority on an instruction fetch request waiting for being input to the primary cache, in an order of the instruction fetch requests of the respective threads that are output from the instruction control unit.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: July 24, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Yuji Shirahige
  • Patent number: 10031754
    Abstract: A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: July 24, 2018
    Assignee: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Patent number: 10031757
    Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level mechanism to overcome a system hang. Such a multi-slice processor includes a plurality of execution slices and a dispatch network of the multi-slice processor implementing a hardware level mechanism to overcome a system hang. Operation of such a multi-slice processor includes, storing, in one or more logical units of a plurality of logical units of an age array, a logical value representing a relative age between instructions; propagating, in response to a current instruction being in a hang state, a hang signal to the plurality of logical units of the age array; in response to the hang signal, generating, from the plurality of logical units, a plurality of logical output values indicating a next instruction ready for execution; and issuing the next instruction for execution.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dhivya Jeganathan, Dung Q. Nguyen, Salim A. Shah
  • Patent number: 10031755
    Abstract: A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: July 24, 2018
    Assignee: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Patent number: 10007518
    Abstract: The number of registers required is reduced by overlapping scalar and vector registers. This also allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are minimized by restricting read access. Dedicated predicate registers reduces requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: June 26, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy David Anderson, Duc Quang Bui, Mel Alan Phipps, Todd T. Hahn, Joseph Zbiciak
  • Patent number: 9983872
    Abstract: An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. A data processor is responsive to the decoded conditional select instruction and the condition (i) having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register, and (ii) not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: May 29, 2018
    Assignee: ARM Limited
    Inventors: Simon John Craske, Richard Roy Grisenthwaite, Nigel John Stephens
  • Patent number: 9965333
    Abstract: A job submission method that presents a set of algorithms that provide automated workload selection to a batch processing system that has the ability to receive and run jobs on various computing resources simultaneously is provided. If all machines in the batch system are running jobs, a queue containing the extra jobs for execution results. For compute intensive workloads, such as chip design, an automated workload selection system software layer submits jobs to the batch processing system. This keeps the batch processing system continually full of useful work The job submission system provides for organizing workloads, assigning relative ratios between workloads, associating arbitrary workload validation algorithms with a workload or parent workload, associating arbitrary selection algorithms with a workload or workload group, defining high priority workloads that preserve fairness and balancing the workload selection based on current status of the batch system, validation status, and the workload ratios.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: May 8, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Richard Reysa, Bryan Ronald Hunt, Stephen McCants, Tierney Bruce McCaughrin, Brain Lee Kozitza
  • Patent number: 9965280
    Abstract: A processor includes a front end to decode an instruction and pass the instruction to execution units with branch suffix information. The processor further includes execution units to execute the instruction and a retirement unit to retire the instruction. The instruction is to specify an operation to be conditionally executed based upon a branch suffix to identify previous execution. The processor further includes logic to, upon retirement of the instruction, determine the result of a series of branch operations preceding execution of the instruction, compare the result to the branch suffix information, allow execution and retirement of the instruction based on a determination that the result matches the branch suffix information, and generate a fault based on a determination that the result does not match the branch suffix information.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 8, 2018
    Assignee: Intel Corporation
    Inventors: Michael F. Spear, Gilles A. Pokam
  • Patent number: 9959117
    Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: May 1, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 9960917
    Abstract: A method is described. The method includes iteratively performing for each position in a result matrix stored in a third register, multiplying a value at a matrix position stored in a first register with a value at a matrix position stored in a second register to obtain a first multiplicative value, where the positions in the first register and the second register are determined by the position in the result matrix and performing an exclusive or (XOR) operation with the first multiplicative value and a value stored at a result matrix position stored in the third register to obtain a result value.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 1, 2018
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Gilbert M. Wolrich, Kirk S. Yap, James D. Guilford, Erdinc Ozturk, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon
  • Patent number: 9959118
    Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 1, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 9952862
    Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwartz, Timothy J. Slegel
  • Patent number: 9946542
    Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Eric M. Schwarz, Timothy J. Slegel
  • Patent number: 9934040
    Abstract: According to an aspect, virtualized weight perceptron branch prediction is provided in a processing system. A selection is performed between two or more history values at different positions of a history vector based on a virtualization map value that maps a first selected history value to a first weight of a plurality of weights, where a number of history values in the history vector is greater than a number of the weights. The first selected history value is applied to the first weight in a perceptron branch predictor to determine a first modified virtualized weight. The first modified virtualized weight is summed with a plurality of modified virtualized weights to produce a prediction direction. The prediction direction is output as a branch predictor result to control instruction fetching in a processor of the processing system.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Matthias D. Heizmann, Daniel Lipetz, Brian R. Prasky
  • Patent number: 9928075
    Abstract: Embodiments relate to load queue entry reuse for operand store compare (OSC) history table update. An aspect includes allocating a load queue entry in a load queue to a load instruction that is issued into an instruction pipeline, the load queue entry comprising a valid tag that is set and a keep tag that is unset. Another aspect includes based on the flushing of the load instruction, unsetting the valid tag and setting the keep tag. Another aspect includes reissuing the load instruction into the instruction pipeline. Another aspect includes based on determining that the allocated load queue entry corresponds to the reissued load instruction, setting the valid tag and leaving the keep tag set. Another aspect includes based on completing the reissued load instruction, and based on the valid tag and the keep tag being set, updating the OSC history table corresponding to the load instruction.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: March 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Khary J. Alexander, Ilya Granovsky