Abstract: An integrated circuit (IC) device includes a first conductive line in a closed curve defining a local area on a substrate. The first conductive line has a first end portion and a second end portion. A second conductive line is outside the local area. The second conductive line has a linear line portion along the closed curve and a bulging end portion along the closed curve. The bulging end portion protrudes from the linear line portion toward the first end portion of the first conductive line in the second lateral direction and protrudes further than the first end portion to the outside of the local area. A method of manufacturing an IC device includes forming a first reference pattern having a mandrel hole. A reference spacer is formed inside the mandrel hole. A second reference pattern is formed. The second reference pattern has a shift hole.

Abstract: A light emitting display device includes first and second pixel circuit portions, each having a transistor with a polycrystalline semiconductor and a transistor with an oxide semiconductor, and first and second light emitting diodes including first and second anodes connected with the first and second pixel circuit portions, respectively. An encapsulation layer covers the first and second pixel circuit portions and the first and second light emitting diodes. A light blocking layer includes first and second light blocking layer openings that are disposed on the encapsulation layer and overlap the first and second anodes, respectively. First and second color filters are disposed in the first and second light blocking layer openings, wherein first and second expansion portions corresponding to the first and second anodes are disposed in a first and second conductive layers disposed first down from the first anode and second down from the second anode, respectively.

Abstract: A display device includes: a substrate; a first conductive layer on the substrate and including a conductive pattern electrically connected to a first transistor; a first organic planarization layer on the first conductive layer; an organic layer on the first organic planarization layer and including a first bank having a first height and a second organic planarization layer having a second height lower than the first height; a first electrode on the organic layer; a second electrode on the organic layer and spaced apart from the first electrode; and a light-emitting element between the first electrode and the second electrode. The first organic planarization layer has a first opening exposing the conductive pattern, and the second organic planarization layer has a second opening exposing the conductive pattern. Sidewalls of the first opening and sidewalls of the second opening are not aligned in line with each other.

Abstract: An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

Abstract: A semiconductor device includes a source structure, first and second stack structures, including first gate electrodes stacked on the source structure to be spaced apart from each other; a dummy structure on the source structure between the first and the second stack structures, and including second gate electrodes stacked to be spaced apart from each other; first separation regions passing through the first and second stack structures, and spaced apart from each other; second separation regions extending between each of the first and second stack structures and the dummy structure; channel structures passing through the first and second stack structures, and respectively including a channel layer, connected to the source structure through the channel layer; and first source contact structures passing through the dummy structure, and respectively including a first contact layer connected to the source structure through a lower surface of the first contact layer.

Abstract: A manufacturing method of a semiconductor package includes the following steps. An encapsulated semiconductor package is provided on a substrate. A heat dissipation sheet is cut into a plurality of heat dissipation films. The plurality of heat dissipation films are attached on the encapsulated semiconductor package, wherein the plurality of heat dissipation films jointly cover an upper surface of the encapsulated semiconductor package. A cover lid is provided on the substrate, wherein the cover lid is in contact with the plurality of heat dissipation films.

Abstract: A substrative patterning process is provided that forms an interconnect structure including a connector tab located between two adjacent electrically conductive line structures. The connector tab and the two adjacent electrically conductive line structures are of unitary construction and are located in a same metallization level.

Abstract: An electrical device includes a substrate, a dielectric layer supported by the substrate, and an electrically conductive vertical interconnect extending through the dielectric layer. The dielectric layer may be formed at low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The dielectric layer may be a low-stress layer that imparts no stress or less stress than a failure stress of fragile material in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at that step. The vertical interconnect may be diffusion bondable with another opposing interconnect at a low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The vertical interconnect may have a coefficient of thermal expansion (CTE) that is greater than a CTE of the dielectric layer to facilitate 3D-integration.

Abstract: A semiconductor device including a first block word line, and a first channel layer located in the first block word line. the semiconductor device including a source pad connected to the first channel layer and located on the first block word line, and a first drain pad connected to the first channel layer and located on the first block word line. The semiconductor device including a global word line connected to the source pad, and a first local word line connected to the first drain pad.

Abstract: A display panel includes: a display substrate including a display area and a pad area spaced apart from a side of the display area in a first direction; and first to (n)th signal pads (where n is an integer of 2 or more) in the pad area on the display substrate, extending in the first direction, and spaced apart from each other in a second direction perpendicular to the first direction, wherein a (k)th signal pad among the first to (n)th signal pads (where k is an integer between 1 and n) is between the first signal pad and the (n)th signal pad, wherein a length of each of (k)th to (n)th signal pads among the first to (n)th signal pads along the first direction gradually increases, and wherein a width of each of the (k)th to (n)th signal pads along the second direction gradually decreases.

Abstract: An imaging device including: a photoelectric converter; a protection member provided on a light incidence side of the photoelectric converter; a substrate opposed to the protection member with the photoelectric converter interposed therebetween and having a first surface on the photoelectric converter side and a second surface opposed to the first surface; a rewiring layer provided in a selective region of the second surface of the substrate; and a protective resin layer provided on the second surface of the substrate, the second surface of the substrate having an external terminal coupling region exposed from the protective resin layer, and a stress relaxation region exposed from the protective resin layer and disposed at a position different from the external terminal coupling region.

Abstract: A display substrate, including: a plurality of sub-pixels arranged on a first surface of a base substrate; and a plurality of signal lines arranged on the base substrate and arranged in the same layer as a source and a drain of a transistor of a pixel driving circuit of the sub-pixel. The plurality of signal lines include at least first signal lines extending in a first direction and are spaced apart in a second direction intersecting the first direction. The plurality of sub-pixels include a first sub-pixel, orthographic projections of two first side edge portions opposite in the second direction of a first electrode of the first sub-pixel on the base substrate partially overlap with orthographic projections of two adjacent first signal lines on the base substrate, respectively, so that a first inclined surface of the first electrode of the first sub-pixel is recessed toward the first surface.

Abstract: A semiconductor device including a substrate including first and second regions along a first direction, and a third region between the first region and the second region, an active pattern extending in the first direction, on the substrate, and first to third gate electrodes spaced apart from each other and extending in a second direction, on the active pattern, the active pattern of the first region including first semiconductor patterns spaced apart from each other and penetrating the first gate electrode, the active pattern of the second region including second semiconductor patterns spaced apart from each other and penetrating the second gate electrode, the active pattern of the third region including a transition pattern protruding from the substrate and intersecting the third gate electrode and including a sacrificial pattern and a third semiconductor pattern alternately stacked on the third region and including different materials from each other.

Abstract: A display panel, a display device, and a manufacturing method of the display panel are provided. The display panel includes a base substrate, a thin film transistor layer, a planarization layer, an anode layer, and a cathode layer. The anode layer includes an anode and a connection portion. A first protruding portion protrudes from the connection portion. The first protruding portion and the planarization layer form an undercut structure. The cathode layer is electrically connected to the connection portion. The undercut structure and the anode layer are formed simultaneously during being performed a patterning process, thereby reducing a number of photomasks.

Abstract: There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a peripheral circuit structure with a page buffer group; a net-shaped first source pattern disposed on the peripheral circuit structure, the net-shaped first source pattern with a plurality of openings; a memory cell array disposed on the net-shaped first source pattern; a second source pattern disposed between the net-shaped first source pattern and the memory cell array; and a cell-array-side pad pattern, disposed between the net-shaped first source pattern and the second source pattern, extending toward the net-shaped first source pattern from the second source pattern, the cell-array-side pad pattern being bonded directly to the net-shaped first source pattern.

Abstract: A display apparatus including a pixel electrode disposed on a substrate, an opposite electrode disposed to face the pixel electrode, a first emission layer and a second emission layer disposed on the first emission layer and overlapping each other between the pixel electrode and the opposite electrode, and a charge generation layer disposed between the first emission layer and the second emission layer, in which the charge generation layer includes an n-type charge generation layer, a p-type charge generation layer, and a metal interlayer disposed between the n-type charge generation layer and the p-type charge generation layer, and the metal interlayer includes metal having a work function of about ?6.0 eV to about ?3.5 eV.

Abstract: Provided is a manufacturing method of a semiconductor device having a semiconductor substrate. The manufacturing method includes forming an interlayer insulating film above the semiconductor substrate; forming a metal electrode above the interlayer insulating film; acquiring an image of the metal electrode and detecting defect candidates on a surface of the metal electrode based on the image; and performing inspection by determining a quality of the semiconductor device, based on height information of each of the detected defect candidates in a direction perpendicular to the surface of the metal electrode.

Abstract: A light emitting element and a display device are discussed. The light emitting element can include a first n-type semiconductor layer, a first light emitting layer disposed on the first n-type semiconductor layer, a first p-type semiconductor layer disposed on the first light emitting layer, a second p-type semiconductor layer disposed on the first p-type semiconductor layer, a bonding layer disposed between the first p-type semiconductor layer and the second p-type semiconductor layer, a second light emitting layer disposed on the second p-type semiconductor layer, a second n-type semiconductor layer disposed on the second light emitting layer, a p-type electrode disposed on the second p-type semiconductor layer, a first n-type electrode disposed on the first n-type semiconductor layer, and a second n-type electrode disposed on the second n-type semiconductor layer.

Abstract: An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.