Abstract: A semiconductor device including a first block word line, and a first channel layer located in the first block word line. the semiconductor device including a source pad connected to the first channel layer and located on the first block word line, and a first drain pad connected to the first channel layer and located on the first block word line. The semiconductor device including a global word line connected to the source pad, and a first local word line connected to the first drain pad.

Abstract: A display panel includes: a display substrate including a display area and a pad area spaced apart from a side of the display area in a first direction; and first to (n)th signal pads (where n is an integer of 2 or more) in the pad area on the display substrate, extending in the first direction, and spaced apart from each other in a second direction perpendicular to the first direction, wherein a (k)th signal pad among the first to (n)th signal pads (where k is an integer between 1 and n) is between the first signal pad and the (n)th signal pad, wherein a length of each of (k)th to (n)th signal pads among the first to (n)th signal pads along the first direction gradually increases, and wherein a width of each of the (k)th to (n)th signal pads along the second direction gradually decreases.

Abstract: An imaging device including: a photoelectric converter; a protection member provided on a light incidence side of the photoelectric converter; a substrate opposed to the protection member with the photoelectric converter interposed therebetween and having a first surface on the photoelectric converter side and a second surface opposed to the first surface; a rewiring layer provided in a selective region of the second surface of the substrate; and a protective resin layer provided on the second surface of the substrate, the second surface of the substrate having an external terminal coupling region exposed from the protective resin layer, and a stress relaxation region exposed from the protective resin layer and disposed at a position different from the external terminal coupling region.

Abstract: A display substrate, including: a plurality of sub-pixels arranged on a first surface of a base substrate; and a plurality of signal lines arranged on the base substrate and arranged in the same layer as a source and a drain of a transistor of a pixel driving circuit of the sub-pixel. The plurality of signal lines include at least first signal lines extending in a first direction and are spaced apart in a second direction intersecting the first direction. The plurality of sub-pixels include a first sub-pixel, orthographic projections of two first side edge portions opposite in the second direction of a first electrode of the first sub-pixel on the base substrate partially overlap with orthographic projections of two adjacent first signal lines on the base substrate, respectively, so that a first inclined surface of the first electrode of the first sub-pixel is recessed toward the first surface.

Abstract: A semiconductor device including a substrate including first and second regions along a first direction, and a third region between the first region and the second region, an active pattern extending in the first direction, on the substrate, and first to third gate electrodes spaced apart from each other and extending in a second direction, on the active pattern, the active pattern of the first region including first semiconductor patterns spaced apart from each other and penetrating the first gate electrode, the active pattern of the second region including second semiconductor patterns spaced apart from each other and penetrating the second gate electrode, the active pattern of the third region including a transition pattern protruding from the substrate and intersecting the third gate electrode and including a sacrificial pattern and a third semiconductor pattern alternately stacked on the third region and including different materials from each other.

Abstract: A display panel, a display device, and a manufacturing method of the display panel are provided. The display panel includes a base substrate, a thin film transistor layer, a planarization layer, an anode layer, and a cathode layer. The anode layer includes an anode and a connection portion. A first protruding portion protrudes from the connection portion. The first protruding portion and the planarization layer form an undercut structure. The cathode layer is electrically connected to the connection portion. The undercut structure and the anode layer are formed simultaneously during being performed a patterning process, thereby reducing a number of photomasks.

Abstract: There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a peripheral circuit structure with a page buffer group; a net-shaped first source pattern disposed on the peripheral circuit structure, the net-shaped first source pattern with a plurality of openings; a memory cell array disposed on the net-shaped first source pattern; a second source pattern disposed between the net-shaped first source pattern and the memory cell array; and a cell-array-side pad pattern, disposed between the net-shaped first source pattern and the second source pattern, extending toward the net-shaped first source pattern from the second source pattern, the cell-array-side pad pattern being bonded directly to the net-shaped first source pattern.

Abstract: A display apparatus including a pixel electrode disposed on a substrate, an opposite electrode disposed to face the pixel electrode, a first emission layer and a second emission layer disposed on the first emission layer and overlapping each other between the pixel electrode and the opposite electrode, and a charge generation layer disposed between the first emission layer and the second emission layer, in which the charge generation layer includes an n-type charge generation layer, a p-type charge generation layer, and a metal interlayer disposed between the n-type charge generation layer and the p-type charge generation layer, and the metal interlayer includes metal having a work function of about ?6.0 eV to about ?3.5 eV.

Abstract: Provided is a manufacturing method of a semiconductor device having a semiconductor substrate. The manufacturing method includes forming an interlayer insulating film above the semiconductor substrate; forming a metal electrode above the interlayer insulating film; acquiring an image of the metal electrode and detecting defect candidates on a surface of the metal electrode based on the image; and performing inspection by determining a quality of the semiconductor device, based on height information of each of the detected defect candidates in a direction perpendicular to the surface of the metal electrode.

Abstract: A light emitting element and a display device are discussed. The light emitting element can include a first n-type semiconductor layer, a first light emitting layer disposed on the first n-type semiconductor layer, a first p-type semiconductor layer disposed on the first light emitting layer, a second p-type semiconductor layer disposed on the first p-type semiconductor layer, a bonding layer disposed between the first p-type semiconductor layer and the second p-type semiconductor layer, a second light emitting layer disposed on the second p-type semiconductor layer, a second n-type semiconductor layer disposed on the second light emitting layer, a p-type electrode disposed on the second p-type semiconductor layer, a first n-type electrode disposed on the first n-type semiconductor layer, and a second n-type electrode disposed on the second n-type semiconductor layer.

Abstract: An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a sub saturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base; a plurality of channel pillars perpendicularly provided on the base; a plurality of parallel bit lines, each of the bit lines wrapping lower parts of one column of the channel pillars; and a plurality of parallel word lines, each of the word lines wrapping upper parts of one row of the channel pillars, where the word lines and the bit lines are perpendicular to each other on a same projection plane; an insulating material layer is formed around the channel pillars below the bit lines, between adjacent bit lines, around the channel pillars between the bit lines and the word lines, and between adjacent word lines, separately; and gaps are formed in at least one of the insulating material layers.

Abstract: A memory device includes a cell region in which memory blocks, respectively including gate electrodes and insulating layers, alternately stacked on a substrate, and channel structures, extending in a first direction, perpendicular to an upper surface of the substrate, passing through the gate electrodes and the insulating layers, and connected to the substrate, are arranged. A peripheral circuit region includes a row decoder connected to the gate electrodes and a page buffer connected to the channel structures. The memory blocks include main blocks and at least one spare block, wherein a length of the spare block is shorter than a length of each of the main blocks, in a second direction, parallel to the upper surface of the substrate.

Abstract: According to an aspect of the present disclosure, the display device includes a stretchable lower substrate and a plurality of first substrates disposed on the lower substrate and in which pixels are disposed. The display device also includes a plurality of second substrates connecting first substrates adjacent to each other among the plurality of first substrates. The display device further includes a plurality of connection lines disposed on the plurality of second substrates and connecting the pixels.

Abstract: A semiconductor substrate includes a first circuit region, a second circuit region, and a third circuit region. A wiring layer includes a first boundary region that includes a first boundary between the first and second circuit regions, a second boundary region that includes a second boundary between the second and the third circuit regions, and a passing wiring region between the first and second boundary regions. The first boundary region includes a first wiring group, the second boundary region includes a second wiring group, and the passing wiring region includes a passing wiring group. The first wiring group, the second wiring group, and the passing wiring group are disposed in a same layer. A wiring disposed in a same layer as the passing wiring group and electrically connected to the second circuit region is included in any one of the first and second wiring groups.

Abstract: The present invention describes electronic devices and compositions that can be used in electronic devices, the electronic devices including a sensitizer and a fluorescent emitter, wherein the sensitizer is a phosphorescent compound and wherein at least one of the two following conditions (I) or (II) must be satisfied, it being preferable when condition (I) is satisfied: S1K(FE)?S1K(S)?X??(I) S1max(FE)?S1max(S)?Y??(II) wherein, e.g., X, Y are each ?0.5 eV; S1K(FE) is the energy of the first excited singlet state of the fluorescent emitter; S1K(S) is the energy of the first excited state of the sensitizer; S1max(FE) is the energy of the first excited singlet state of the fluorescent emitter; S1max(S) is the energy of the first excited state of the sensitizer; and wherein the photoluminescence spectra of the sensitizer and of the fluorescent emitter are determined at room temperature.

Abstract: A thin-film transistor substrate includes an insulating substrate, a conductor layer including a top-gate electrode part of an oxide semiconductor thin-film transistor, an oxide semiconductor layer located lower than the top-gate electrode part and including a channel region of the oxide semiconductor thin-film transistor, and an upper insulating layer located between the conductor layer and the oxide semiconductor layer. The oxide semiconductor layer includes low-resistive regions lower in resistance than the channel region. The low-resistive regions sandwich the channel region in an in-plane direction of the insulating substrate and contain impurities to cause resistance reduction of the low-resistive regions. A concentration profile in a layering direction of the impurities to cause resistance reduction of the low resistive regions has one or more peaks. The one or more peaks are located outside the oxide semiconductor layer.

Abstract: Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate including first and second trench isolation regions positioned in the semiconductor substrate. The first trench isolation region extends to a first depth in the semiconductor substrate, and the second trench isolation region extends to a second depth in the semiconductor substrate. The second depth is greater than the first depth. A bipolar junction transistor structure includes a collector, an emitter, and a base each disposed in the semiconductor substrate. The collector includes a portion that extends to the top surface of the semiconductor substrate, the first trench isolation region is positioned in the base, the second trench isolation region is positioned in a lateral direction between the portion of the collector and the base, and the second trench isolation region surrounds the base, the emitter, and the first trench isolation region.

Abstract: A semiconductor device including an etch stop layer and a method of forming is provided. The semiconductor device may include a source/drain region and a gate structure, wherein a first etch stop layer is over a conductive plug to a source/drain region and a second etch stop layer is over the gate structure. The first etch stop layer and the second etch stop layer may have different thicknesses. A dielectric layer may be formed over the first etch stop layer and the second etch stop layer, and contacts may be formed through the dielectric layer and the first and second etch stop layers.