Patents Examined by John R. Lastova
  • Patent number: 4914603
    Abstract: A method of training an artificial neural network uses a computer configured as a plurality of interconnected neural units arranged in a layered network including an input layer having a network input, and an output layer having a network output. A neural unit has a first subunit and a second subunit. The first subunit having one or more first inputs, and a corresponding first set of variables for operating upon the first inputs to provide a first output. The first set of variables can change in response to feedback representing differences between desired network outputs for selected network inputs and actual network outputs. The second subunit has a plurality of second inputs, and a corresponding second set of variables for operating upon said second inputs to provide a second output. The second set of variables can change in response to differences between desired network outputs for selected network inputs and actual network outputs.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: April 3, 1990
    Assignee: GTE Laboratories Incorporated
    Inventor: Laurence F. Wood
  • Patent number: 4912649
    Abstract: A method of accelerating the training of an artificial neural network uses a computer configured as an artificial neural network with a network input and a network output, and having a plurality of interconnected units arranged in layers including an input layer and an output layer. Each unit has a multiplicity of unit inputs and a set of variables for operating upon the unit inputs to provide a unit output. A plurality of examples are serially provided to the network input and the network output is observed. The computer is programmed with a back propagation algorithm for adjusting each set of variables in response to feedback representing differences between the network output for each example and the desired output. The examples are iterated while those values which change are identified. The examples are reiterated and the algorithm is applied to only those values which changed in a previous iteration.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: March 27, 1990
    Assignee: GTE Government Systems Corporation
    Inventor: Laurence F. Wood
  • Patent number: 4912655
    Abstract: A method of accelerating the training of an artificial neural network uses a computer configured as an artificial neural network with a network input and a network output, and having a plurality of interconnected units arranged in layers including an input layer and an output layer. Each unit has a multiplicity of unit inputs and a set of variables for operating upon a unit inputs to provide a unit output. The computer is programmed with a back propagation algorithm. A plurality of examples are serially provided to the network input and the network output is observed. The examples are iterated and proposed changes to each set of variables are calculated in response to feedback representing differences betwen the network output for each example and the desired output. The proposed changes are accumulated for a predetermined number of iterations, whereupon the accumulated proposed changes are added to the set of variables.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: March 27, 1990
    Assignee: GTE Laboratories Incorporated
    Inventor: Laurence F. Wood
  • Patent number: 4912651
    Abstract: A method of accelerating the training of an artificial neural network uses a computer configured as an artificial neural network with a network input and a network output, and having a plurality of interconnected units arranged in layers including an input layer and an output layer. Each unit has a multiplicity of unit inputs and a set of variables for operating upon a unit inputs to provide a unit output. A plurality of examples are serially provided to the network input and the network output is observed. The computer is programmed with a back propagation algorithm for adjusting each set of variables in response to feedback representing differences between the network output for each example and the desired output. The examples are iterated until the signs of the outputs of the units of the output layer converge. Then each set of variables is multiplied by a multiplier. The examples are reiterated until the magnitude of the outputs of the units of the output layer converge.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: March 27, 1990
    Assignee: GTE Laboratories Incorporated
    Inventors: Laurence F. Wood, Michael J. Grimaldi, Eric D. Peterson
  • Patent number: 4912653
    Abstract: A trainable artificial neural network includes a computer configured as a plurality of interconnected neural units arranged in a layered network. An input layer has a network input and an output layer has a network output. A neural unit has a first subunit and a second subunit, with the first subunit having one or more first inputs and a corresponding first set of variables for operating upon the said first inputs to provide a first output. The first set of variables can change in response to feedback representing differences between desired network outputs and actual network outputs. The second subunit has a plurality second inputs, and a corresponding second set of variables for operating upon said second inputs to provide a second output. The second set of variables can change in response to differences between desired network outputs for selected network inputs and actual network outputs.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: March 27, 1990
    Assignee: GTE Laboratories Incorporated
    Inventor: Laurence F. Wood
  • Patent number: 4912654
    Abstract: A method of accelerating the training of an artificial neural network uses a computer configured as an artificial neural network with a network input and a network output, and having a plurality of interconnected units arranged in layers including an input layer and an output layer. Each unit has a multiplicity of unit inputs and a set of variables for operating upon a unit inputs to provide a unit output in the range positive 1 and negative 1. A plurality of examples are serially provided to the network input and the network output is observed. The computer is programmed with a back propagation algorithm for calculating changes to the sets of variables in response to feedback representing differences between the network output for each example and the desired output. The absolute magnitude of the product of an input and the corresponding output of a unit is calculated.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: March 27, 1990
    Assignee: Government Systems Corporation GTE
    Inventor: Laurence F. Wood
  • Patent number: 4912652
    Abstract: A method of accelerating the training of an artificial neural network uses a computer configured as an artificial neural network with a network input and a network output and having a plurality of interconnected units arranged in layers including an input layer and an output layer. Each unit has a multiplicity of unit inputs and a set of variables for operating upon a unit inputs to provide a unit output in the range between binary 1 and binary 0. A plurality of training examples is serially provided to the network input and the network output is observed. The computer is programmed with a back propagation algorithm for changing each set of variables in response to feedback representing differences between the network output for each example and the desired output. The examples are iterated while the output of a unit is observed.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: March 27, 1990
    Assignee: GTE Laboratories Incorporated
    Inventor: Laurence F. Wood
  • Patent number: 4912647
    Abstract: A method of training an artificial neural network uses a first computer configured as a plurality of interconnected neural units arranged in a network. A neural unit has a first subunit and a second subunit. The first subunit has first inputs and a corresponding first set of variables for operating upon the first inputs to provide a first output during a forward pass. The first set of variables can change in response to feedback representing differences between desired network outputs and actual network outputs. The second subunit has a plurality of second inputs, and a corresponding second set of variables for operating upon the second inputs to provide a second output. The second set of variables can change in response to differences between desired network outputs for selected network inputs and actual network outputs. The computer provides an activating variable representing the difference between current second output and previous second outputs.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: March 27, 1990
    Assignee: GTE Laboratories Incorporated
    Inventor: Laurence F. Wood
  • Patent number: 4910658
    Abstract: A process control system for monitoring and controlling elements of a process. A control unit is electrically connected to a multi-conductor cable upon which are removably connected in series configuration a plurality of serially addressable control modules. The control modules are removably connected to elements of the controlled process to permit monitoring and control of the elements. The modules may be readily connected to or removed from the process elements and multi-conductor cable, to permit expansion or modification of the control system as needed for proper use in controlling process systems. The control modules operate independently from outside signals in monitoring the process elements, and respond to selected element status conditions by accessing communication with the central controller on a priority basis over other control modules in the system. The control unit includes a touch sensitive video screen for providing information to an receiving instructions from a user.
    Type: Grant
    Filed: September 27, 1988
    Date of Patent: March 20, 1990
    Assignee: Eaton Leonard Technologies, Inc.
    Inventors: George M. Dudash, Joseph J. Kirby
  • Patent number: 4907146
    Abstract: A software-independent network which enables interconnection at video and keyboard level between one master computer and several slave computers, and is compatible with computers using either digital or analog video output. Hardware includes a master control box, and a plurality of switching circuits (one serving each slave computer) all of which are connected in cascade to the master control box by a single multicore cable; both master and slave units are interfaced with the relative computers via their standard VDU and keyboard connectors. Video images can be sent back and forth between instructor and students, the instructor can edit the screen of a student selected, or the student can edit the master screen, and a copy of the video image under scrutiny can be broadcast to all the students.
    Type: Grant
    Filed: October 6, 1987
    Date of Patent: March 6, 1990
    Assignee: Giancarlo Caporali
    Inventor: Giancarlo Caporali
  • Patent number: 4906418
    Abstract: A method for teaching a machining line to be machined is disclosed. A borderline is formed along the machining line on a workpiece. Then, a borderline sensor is moved across the borderline at each sensing position. The positions of the sensor are stored as a teaching position at each time when the borderline is detected by the sensor. The sensing interval between each teaching position is automatically adjusted according to the change in the curvature of the borderline. At the place where the curvature of the borderline becomes large, the sensing interval is shortened in order to maintain teaching accuracy.
    Type: Grant
    Filed: October 24, 1988
    Date of Patent: March 6, 1990
    Assignee: Toyoda-Koki Kabushiki-Kaisha
    Inventors: Yasufumi Tokura, Shigeo Hotta, Osamu Matsuda, Hajime Fukami
  • Patent number: 4903192
    Abstract: A PID controller system comprises a PID controller for PID controlling a process standing for an object to be controlled, and an automatic adjuster being responsive to a variable relating to the manipulation of the PID controller and the response shape of the control variable from the process to obtain necessary performance indexes and preparing, on the basis of the performance indexes, optimum control parameters for tuning the actual control variable to the control command value, the optimum control parameters being fedback from the automatic adjuster to the PID controller.
    Type: Grant
    Filed: April 1, 1988
    Date of Patent: February 20, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Tadayoshi Saito, Junzo Kawakami, Susumu Takahashi, Testuo Suehiro, Hiroshi Matsumoto, Kouji Tachibana
  • Patent number: 4896284
    Abstract: A semiconductor integrated circuit so arranged that selection is made out of output signals of a decision circuit which determines the levels of analog values inputted as an object for multiplication and multiplication is carried out with respect to the selected signal and the digital value inputted as an object for multiplication, the result of the multiplication being added with the digital value as shifted to the higher position of specified bits, a multiplication result being thereby calculated with respect to the analog value and the digital value, whereby the required area of wiring connections is reasonably reduced and faster operation is assured.
    Type: Grant
    Filed: August 1, 1988
    Date of Patent: January 23, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Sumitaka Takeuchi, Keisuke Okada, Masatoshi Kimura
  • Patent number: 4896322
    Abstract: In a circuit configuration and a method for testing storage cells, all of the bit lines lead to one pair of fault lines which is first precharged with mutually-complementary logic levels. All of the storage cells of a word line are always read-out in parallel relative to one another. In the event of "no fault" the pair of fault lines retains its logic states, whereas in the case of a fault one of the fault lines changes its logic state through switching transistors. This is recognized and analyzed by a comparator circuit in the form of an XOR-circuit or an XNOR-circuit.
    Type: Grant
    Filed: March 16, 1988
    Date of Patent: January 23, 1990
    Assignee: Siemens Atkiengesellschaft
    Inventors: Rainer Kraus, Oskar Kowarik, Kurt Hoffmann, Manfred Paul
  • Patent number: 4894830
    Abstract: A plurality of first flip-flop circuits are provided having outputs connected respectively to inputs of a logic circuit. During a test mode, scan data is first loaded into the flip-flop circuits to activate desired logical paths in the logic circuit and subsequently a pulse is scanned across the first flip-flop circuits to cause successive reversals to occur in the stored scan data. As a result, test signals can propagate through the activated logical paths. Connected to the outputs of the logic circuit are a plurality of second flip-flop circuits which are configured into a linear feedback shift register during the test mode to enable a test circuit to observe its serial output to determine the dynamic performance of the logic circuit.
    Type: Grant
    Filed: January 19, 1988
    Date of Patent: January 16, 1990
    Assignee: NEC Corporation
    Inventor: Masato Kawai
  • Patent number: 4893230
    Abstract: A physical quantity controller is provided which includes numeral updating keys, a mode changing key, and a display unit. A value displayed on the display unit is updated via the numeral updating keys. The updated value is automatically set as a new set point or alarm point when a predetermined time elapses after the updating keys are actuated.
    Type: Grant
    Filed: March 24, 1988
    Date of Patent: January 9, 1990
    Assignee: Omron Tateisi Electronics Co.
    Inventors: Tooru Shimomura, Kazutomo Naganawa, Toshiya Tanamura, Toshiaki Nagao
  • Patent number: 4893255
    Abstract: Pulse trains are utilized for the transmission of information in a neural network. A squash function is achieved by logically OR'ing together pulsed outputs, giving f(x) approximately 1-e.sup.-x. For Back Propagation, as derived by Rumelhart, the derivative of the squash function is available by examining the time when no OR'ed together pulses are present, being 1-f(x), or e.sup.-x. Logically AND'ing of the two signals. Mulitplication of input frequencies by weights is accomplished by modulating the width of the output pulses, while keeping the frequency the same.
    Type: Grant
    Filed: May 31, 1988
    Date of Patent: January 9, 1990
    Assignee: Analog Intelligence Corp.
    Inventor: Max S. Tomlinson, Jr.
  • Patent number: 4891810
    Abstract: The invention pertains mainly to a reconfigurable computing device. The main object of the invention is a computer comprising redundant elements. The computer according to the present invention can function when there is a failure of one of the elements that constitute it. In this case, the redundant element takes the place of the malfunctioning element. Should the computer according to the present invention be in a critical stage, i.e. a situation where any interruption in computation would have serious consequences, the reconfiguring of the system is postponed to a later instant corresponding to the end of the critical stage. The invention applies mainly to the performing of digital computations.
    Type: Grant
    Filed: October 27, 1987
    Date of Patent: January 2, 1990
    Assignee: Thomson-CSF
    Inventors: Patrick de Corlieu, Michel Prevost, Arnaud du Chene
  • Patent number: 4891763
    Abstract: An automatic programming device has a display structure, an input structure for entering graphical data in accordance with information that is displayed by the display, and a threshold level variation device for varying a threshold level which forms a reference for rounding-off numerical calculation errors during graphical data processing. The programming device also has a reading structure for reading an NC program created in NC data, and a calculator which analyzes the NC program read via the reading structure, generates pattern information specified by each graphical element of points, line segments and circular arcs, and generates tool path information specifying the sequence of tool progress on the pattern.
    Type: Grant
    Filed: April 23, 1987
    Date of Patent: January 2, 1990
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Jyuzo Kuriyama
  • Patent number: 4887219
    Abstract: A board cut-off saw apparatus 10 is described for enabling cut-off saw operator to cross cut boards along their length to obtain usable wood pieces and to remove or discard defective sections. The apparatus 10 includes a plurality of cut-off saw lines 26 with manually activated cut-off saws for cutting the boards along each line. The length of the boards and the length of the cut wood pieces are measured while the board is being cut. Each cut-off saw line has an optical measuring system extending upstream and downstream for measuring the length of the boards 12 and cut wood pieces 24, respectively. The downstream optical sensors (photo) comprise a longitudinal row of closely assembled light emitting diodes 58 for sensing the length of the wood pieces with a measurement resolution of less than 1/4 of an inch. Each cut-off saw line 26 has a sorter for sorting the wood pieces according to their measured length.
    Type: Grant
    Filed: February 2, 1988
    Date of Patent: December 12, 1989
    Assignee: Strauser Manufacturing, Inc.
    Inventor: Michael Strauser