Abstract: A method and a device for the formation of holes in a layer of photosensitive material, in particular for the manufacture of electron sources.This method is characterized in that a membrane (121) with micro-perforations (122) is laid onto the layer of photosensitive material (120); the layer of photosensitive material is insolated through the membrane (121) in order to print areas (125) corresponding to the micro-perforations (122); the membrane (121) is separated from the layer of photosensitive material (120) thus insolated and the photosensitive layer (120) is then developed in order to form holes in it corresponding to the insolated areas (125).
Abstract: An image forming method comprising developing a silver halide photographic light-sensitive material which comprises a support having thereon at least one light-sensitive silver halide emulsion layer: wherein the silver halide photographic light-sensitive material contains at least one kind of hydrazine derivative represented by general formula (NB) in at least one layer of the silver halide emulsion layer(s) and other hydrophilic colloidal layers:A--(B).sub.m (NB)and wherein the development is conducted by using a developing solution having a pH of from not less than 8.5 to less than 11.0, which developing solution does not substantially contain a dihydroxybenzene developing agent, but contains a developing agent represented by general formula (1): ##STR1## The symbols used in the above formulas are defined in the specification.
Abstract: An authenticating pattern 20 for valuable objects is fabricated as an integrated structure of a substrate layer 21 and a transparent overcoat layer 22 with a viewable interface therebetween containing a light diffracting structure 10. Unique parameters are randomly defined in the light diffracting structure by anisotropic process steps not under full control of the producer during the manufacturing of the diffracting structure to prevent copying or creating an exact replica thereof. The resultant uniquely coloured authenticating pattern can be verified by simple observation with the naked eye which is a prerequisite for ubiquitous verification.
Type:
Grant
Filed:
January 10, 1997
Date of Patent:
January 5, 1999
Assignee:
International Business Machines Corporation
Abstract: A diffusion confirming pattern for measuring a diffusion distance of an etch-resistant component during a transfer process of a semiconductor device, includes a first photoresist pattern formed on a substrate according to a first mask pattern, and a second photoresist pattern formed on the substrate according to a second mask pattern, wherein the first mask pattern is separated from the second mask pattern by a predetermined interval, the second photoresist pattern is separated from the first photoresist pattern by an interval, and the predetermined interval is compared with the interval between the first and second photoresist patterns to determine the diffusion distance of the etch-resistant component.
Abstract: A method for controlling the interface in a composite between the matrix material and reinforcing filaments or fibers in a composite structure which comprises the application of a patterned coating or combination of coatings on the reinforcing filaments or fibers to vary the bond between the reinforcement and the matrix. Proportioning of weak- and strong-bonded areas, their respective strengths, and design of bonding patterns can be tailored to the materials requirements of the composite.This method can be employed to prepare metal, ceramic and polymer matrix composites.
Type:
Grant
Filed:
May 27, 1997
Date of Patent:
December 22, 1998
Assignee:
The United States of America as represented by the Secretary of the Air Force
Abstract: A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: 1) holding individual chips for batch processing, 2) depositing a dielectric passivation layer on the top and sidewalls of the chips, 3) opening vias in the dielectric, 4) forming the interconnects by laser pantography, and 5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume.
Abstract: An assemblage useful for autoradiography comprising, in order, a sample layer containing a radioactively labeled biological sample in contact with a phosphor layer, a film layer and a reflector layer. The phosphor layer is preferably a gadolinium oxysulfide containing layer and the film is preferably a photographic film containing a tabular grain emulsion.