Abstract: A high speed comparator comprising an operational amplifier and two inverter portions is provided. The output voltage of the operational amplifier biases a control transistor coupled to the first inverter portion which is coupled to the operational amplifier in a closed loop. A stable reference voltage is coupled to an input of the operational amplifier and forces the switch point of the first inverter to be at the reference voltage. If the second inverter portion comprises transistors having the gate dimensions thereof sized the same as the transistors of the first inverter portion, the switch point of the second inverter is also at the reference voltage. The switch point of the fast comparator has thereby been isolated from process and temperature variations.

Abstract: A method and apparatus are described for developing a series of synchronizing pulses related to a series of input pulses of variable amplitude above a background noise level. A first signal is developed proportional to the derivative of the rising or falling portion (or both) of each of the input pulses. A second signal is developed related to the first signal and having a decay characteristic such that the amplitude of the second signal becomes equal to the amplitude of the first signal at a threshold point which is proportional to the amplitude of the first signal. The synchronizing pulses are developed related to respective threshold points whereby the phase of the synchronizing signal is not dependent on the amplitude of the input pulses.

Abstract: A bucket brigade circuit is described for generating a sequence of packets of charge carriers of the form Q.sub.R /2, Q.sub.R /4, Q.sub.R /8....Q.sub.R /2.sup.N where N is an integer. The charge packets thus generated can be employed in combinations in either digital-to-analog or analog-to-digital converters. The charge generation circuit requires two equal capacitors which are used for charge redistribution. To obtain accurate quantities of charge in the generated charge packets the capacitors employed should be large, however the use of large capacitors results in low operating speed because of the large charge transfer time constants involved. The described circuit provides a scheme to reduce charge transfer time constants and therefore obtain greater speed while still permitting the use of large capacitors for high accuracy.