Abstract: A low capacitance impedance emulator suitable for active conductor termination. The impedance emulator includes an emulating FET and a control circuit coupled to the gate of the emulating FET for maintaining the FET in a linear region of operation. The control circuit includes a control FET, an impedance setting resistor, and an amplifier. The control FET is driven in a closed-loop fashion so that the impedance of the control FET has a known relationship with respect to that of the resistor. The output of the amplifier controls the conduction of both the emulating and control FETs so that the emulating FET provides an impedance proportional to that of the control FET and thus, related to the impedance of the resistor. A disconnect feature is provided, whereby the impedance emulator is responsive to a disconnect signal for disconnecting the impedance provided by the emulating FET.

Abstract: The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources.