Patents Examined by Jonathan Hach
  • Patent number: 6200868
    Abstract: A side insulation layer is formed on a side wall of a gate electrode by oxidizing (or nitrizing) a substance of the gate electrode, so that the gate electrode is insulated from the semiconductor substrate with the side insulation layer and a gate insulation film. The gap between the gate electrode and the semiconductor substrate is greater around the side wall of the gate electrode than around the center thereof. The gap between the side wall of the gate electrode and the semiconductor substrate is densely filled with an insulating substance.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: March 13, 2001
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Akira Mase, Tomoyoshi Kushida
  • Patent number: 6187641
    Abstract: A MOSFET (100) having a heterostructure raised source/drain region and method of making the same. A two layer raised source drain region (106) is located adjacent a gate structure (112). The first layer (106a) is a barrier layer comprising a first material (e.g., SiGe, SiC). The second layer (106b) comprises a second, different material (e.g. Si). The material of the barrier layer (106a) is chosen to provide an energy band barrier between the raised source/drain region (106) and the channel region (108).
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: February 13, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Mark S. Rodder, William U. Liu
  • Patent number: 6177287
    Abstract: A method of reviewing classification data and image data for defects detected in a series of semiconductor manufacturing processes. An inspection wafer is selected from a production lot of wafers and is inspected after the completion of each of the series of semiconductor manufacturing processes. The classification data for each defect is sent to a defect management system and an image for selected defects is sent to an image storage system. Identification data is sent to the defect management system and the image storage system. The image storage system sends a cookie to the defect management system allowing the defect management system to identify defects having an image. A operator controlled review station allows an operator to select defects for review that have an image available for review.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: January 23, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul J. Steffan, Allen S. Yu
  • Patent number: 6162689
    Abstract: High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. Emdodiments include forming field oxide regions, gates, spacers, and lightly doped implants, and then depositing a layer of oxide on a substrate. The oxide layer is masked to protect portions of the oxide layer located near the gate, where it is desired to have a shallow junction, then etched to expose portions of the intended source/drain regions where the silicided contacts are to be formed. A high-dosage source/drain implant is thereafter carried out to form deep source/drain junctions with the substrate where the oxide layer has been etched away, and to form shallower junctions near the gates, where the implant must travel through the oxide layer before reaching the substrate. A layer of cobalt is thereafter deposited and silicidation is performed to form metal silicide contacts over only the deep source/drain junctions, while the cobalt on the oxide layer (i.e.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: December 19, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nick Kepler, Karsten Wieczorek, Larry Wang, Paul Raymond Besser