Abstract: A method of fabricating an integrated circuit with ultra-shallow source and drain junctions utilizes a damascene process. The substrate is over-etched to form extensions in the source and drain regions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract: An integrated circuit and method of fabrication is provided for an integrated circuit having punch-through suppression. Unlike conventional methods of punch-through suppression wherein a dopant implant is fabricated in the device, the present invention utilizes an inert ion implantation process whereby inert ions are implanted through a fabricated gate structure on the semiconductor substrate to form a region of inert ion implant between source and drain regions of a device on the integrated circuit. This accumulation region prevents punch-through between source and drain regions of the device. In a second embodiment, the inert ion implantation is used in conjunction with the conventional punch-through dopant implant. In this second embodiment, diffusion of the implant during subsequent thermal annealing is suppressed by the inert ion accumulation in the subsurface region of the device.

Abstract: Method of manufacturing the quality of contacts e.g. in an LCD module in which an IC is so placed on the surface of a substrate that the external connections of the IC electrically contact the desired interconnections on the substrate. The quality of the electrical contacts is tested by powering up the IC and running a selftest program. This selftest checks all contacts between the external connections of the device and the interconnections on the substrate, e.g. the row-column conductors on the LCD-glass. Due to a possibly poor ohmic contact the signals from the driver-IC may be delayed, the delay measured being representative for the quality of the contact.

Abstract: Methods of forming integrated circuitry, methods of forming elevated source/drain regions, and methods of forming field effect transistors are described. In one embodiment, a transistor gate line is formed over a semiconductive substrate. A layer comprising undoped semiconductive material is formed laterally proximate the transistor gate line and joins with semiconductive material of the substrate and comprises elevated source/drain material for a transistor of the line. Subsequently, conductivity-modifying impurity is provided into the elevated source/drain material. In another embodiment, a common step is utilized to provide conductivity enhancing impurity into both elevated source/drain material and material of the gate line. In another embodiment, the undoped semiconductive layer is first patterned and etched to provide elevated source/drain regions prior to provision of the conductivity-modifying impurity.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor. A substrate having a gate structure is provided. The method of the invention includes forming a liner spacer on each side of the gate structure and a low dopant density region deep inside the substrate. The low dopant density region has a lower dopant density than that of a lightly doped region of the MOS transistor. Then a interchangeable source/drain region with a lightly doped drain (LDD) structure and an anti-punch-through region is formed on each side of the gate structure in the low dopant density region. The depth of the interchangeable source/drain region is not necessary to be shallow.

Abstract: A method for reducing salicide lateral growth. A substrate having a gate structure and an anti-reflection layer on the gate structure is provided. A spacer is formed on the side wall of the gate structure and the anti-reflection layer. Then, the anti-reflection layer is removed to expose the gate structure; wherein the gate structure and the spacers together form a recess structure. A salicide layer is formed on the gate structure in the recess structure and on the substrate.

Abstract: The invention broadens the range of materials and processes that are available for Thin Film Transistor (TFT) devices by providing in the device structure an organic semiconductor layer that is in contact with an inorganic mixed oxide gate insulator involving room temperature processing at up to 150 degrees C. A TFT of the invention has a pentacene semiconductor layer in contact with a barium zirconate titanate gate oxide layer formed on a polycarbonate transparent substrate employing at least one of the techniques of sputtering, evaporation and laser ablation.

Abstract: A method of forming a gate electrode of a compound semiconductor device includes forming a first insulating film pattern having a first aperture, forming a second insulating film pattern having a second aperture consisting of inverse V-type on the first insulating film pattern, forming a T-type gate electrode by depositing a conductivity film on the entire structure, removing a second insulating film pattern, forming a insulating spacer on a pole sidewall by etching a first insulating film pattern, and forming an ohmic electrode of the source and drain by self-aligning method using T-type gate electrode as a mask. Thereby T-type gate electrode of materials such as refractory metals can be prevented to be deteriorate because of high annealing, as well as it is stably formed, by using an insulating film. Ohmic metal and gate electrodes formed by self-aligning method can be prevented an interconnection by forming an insulating film spacer between these electrodes.

Abstract: A semiconductor device is provided and formed using self-aligned low-resistance gates within a metal-oxide semiconductor (MOS) process. A sacrificial dielectric gate structure is formed on a semiconductor substrate instead of a conventional gate dielectric/gate conductor stack. After forming junction regions within a semiconductor substrate, the gate structure is removed to form a trench within a dielectric formed above the substrate. A low-resistance gate material can then be arranged within the trench, i.e., in the region removed of the gate conductor. The gate material can take various forms, including a single layer or multiple metal and/or dielectric layers interposed throughout the as-filled trench. The gate formation occurs after high temperature cycles often associated with activating the previously implanted junctions or growing gate dielectrics. Thus, low-temperature metals such as copper or copper alloys can be used.

Abstract: A method for manufacturing a gate terminal comprising the steps of providing a substrate, then forming and patterning an oxide layer to form a gate region. Next, a gate oxide layer and a crystalline silicon layer are formed in the gate region. This is followed by depositing a tungsten layer in the gate region, and then polishing the tungsten layer to form a final tungsten layer functioning as the gate electrode. Finally, the oxide layer is removed. The method of this invention is able to control the dimensions of the gate terminal produced. Moreover, the formation of a thin crystalline silicon layer over the gate oxide layer helps to increase the bonding strength with the metallic layer, and that the gate electrode can be formed at a lower processing temperature. Therefore, the gate so formed has a higher quality and the processing of the semiconductor is much easier. Furthermore, the silicon nitride layer can serve as an etching stop layer during the etching operation of the oxide layer.

Abstract: In insulated-gate, field effect transistor (IGFET) devices fabricated in integrated circuits, the scaling down of the dimensions of the devices has resulted in structures with dimensions are so small that reproducibility of parameters can become problematic. Specifically, the gate dielectric, typically silicon nitride, silicon oxide or silicon nitride, of a gate structure is nearing the point where the required thickness of the gate dielectric to provide the selected electric field in the channel region is implemented with a few to several atomic layers. In order to improve parameter reproducibility, a dielectric material, such TaO5 or a ferroelectric material, is used as a gate dielectric. TaO5 and the ferroelectric materials have a dielectric constant an order of magnitude higher than the material typically used in the past. Using these materials, the gate dielectric can be proportionately thicker, thereby improving the parameter reproducibility.

Abstract: A system and method of controlling multi-process, multi-product semiconductor fabrication tools. Individual, grouped, or composite controllers are designated to control various tool operations. First control parameters for a fabrication tool process are generated, where the first control parameters are based on first tool operation attributes. Second control parameters for the process are generated based on second tool operation attributes. The fabrication tool is then controlled by generating cooperative control parameters which are a function of the first and second control parameters. Disturbance information can be shared between controllers for use in generating the first and second control parameters while taking into account disturbance information already discovered and quantified.

Abstract: A method of fabricating a gate electrode having dual gate insulating film includes the steps of sequentially providing a substrate having a first portion and a second portion, forming a first insulating film on the first portion of substrate, a first conductive film on the first insulating film and a second insulating film on the first conductive film, forming a third insulating film on the second portion of the substrate, forming a second conductive film on the second and the third insulating films, and patterning the first and the second conductive film to form a gate electrode.

Abstract: A fabrication method of a semiconductor device with an IGFET is provided, which makes it possible to decrease the current leakage due to electrical short-circuit between a gate electrode and source/drain regions of the IGFET through conductive grains deposited on its dielectric sidewalls. After the basic structure of the IGFET is formed, first and second single-crystal Si epitaxial layers are respectively formed on the first and second source/drain regions by a selective epitaxial growth process. Then, the surface areas of the first and second single-crystal Si epitaxial layers are oxidized, and the oxidized surface areas of the first and second single-crystal Si epitaxial layers are removed by etching.

Abstract: A process of forming a silicon thin film includes the steps of: irradiating a pulsed rectangular ultraviolet beam on an amorphous or polycrystalline silicon layer formed on a base body, to thereby form a silicon thin film composed of a group of silicon single crystal grains which are each approximately rectangular-shaped and which are arranged in a grid pattern on the base body. In this process, the moved amount of a ultraviolet beam irradiating position in a period from completion of an irradiation of the rectangular ultraviolet beam to starting of the next irradiation of the rectangular ultraviolet beam is specified at 40 &mgr;m or less, and a ratio of the moved amount to a width of the rectangular ultraviolet beam measured in the movement direction thereof is in a range of 0.1 to 5%. Further, a selected orientation of the silicon single crystal grains to the surface of the base body is approximately the <100> direction.

Abstract: A structure is provided comprising a semiconductor substrate, a gate oxide layer on the substrate, and a polysilicon layer on the gate oxide layer. A masking layer is formed on the polysilicon layer. The masking layer is then patterned into a mask utilizing conventional photolithographic techniques, but without patterning the polysilicon layer. The photoresist layer is then removed, whereafter the mask, which is patterned out of the masking layer, is utilized for patterning the polysilicon layer. The use of a carbon free mask for patterning the polysilicon layer, instead of a conventional photoresist layer containing carbon, results in less breakthrough through the gate oxide layer when the polysilicon layer is patterned. Less breakthrough through the gate oxide layer allows for the use of thinner gate oxide layers, and finally fabricated transistors having lower threshold voltages.

Abstract: Low resistivity contacts are formed on source/drain regions and gate electrodes at a suitable thickness to reduce parasitic series resistances, thereby significantly reducing consumption of underlying silicon, while significantly reducing junction leakage. Embodiments include selectively depositing a metal layer, such as nickel, on the source/drain regions and on the gate electrode and ion implanting to form a barrier layer within the nickel layers which does not react with silicon or nickel silicide during subsequent solicitation. The barrier layer confines salicidation to the relatively thin underlayer layer of nickel, thereby minimizing consumption of underlying silicon while the unsilicidized overlying nickel on the barrier layer ensures low sheet resistivity.

Abstract: A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A dielectric layer is then formed on the surface of the substrate, portions of which are then etched to define a channel opening for the device. A uniform nitride layer is formed over the surface of the substrate. The nitride layer is then etched to create nitride sidewall spacers. Additionally, the channel region is then etched to remove the doped portions of the active region. A gate dielectric is then formed, the gate dielectric including a nitrogen bearing oxide and a high K material. A gate conductor is then formed upon the high K material. A silicidation step is then performed. In alternative embodiments, the source/drain region is not formed and the source and drain are doped after the gate is complete. In the embodiment, the gate resides upon the active region and etching into the active region is not required.

Abstract: Channel doping is implemented such that dopants remain localized under the gate without migrating under the source/drain juctions during processing, thereby avoiding performance degradation of the finished device. Embodiments include implanting impurities at an acute angle to form a lateral channel implant localized below the gate after activation of source/drain regions, and activating the lateral channel implant by a low-temperature RTA during subsequent metal silicide formation. The use of a low-temperature RTA for electrical activation of the lateral channel implant avoids impurity migration under the source/drain junctions, thereby lowering parasitic junction capacitance and enabling the manufacture of semiconductor devices exhibiting higher circuit speeds with improved threshold voltage control.

Abstract: Detection of the endpoint for removal of a target film overlying a stopping film by removing the target film with a process that selectively generates a chemical reaction product (for example ammonia when polishing a wafer with a nitride film in a slurry containing KOH) with either the target or stopping film, and monitoring the level of chemical reaction product as the target film is removed. Also, detection of a substance at very low concentrations in a liquid, by extracting the substance present as a gas from the liquid and monitoring the gas to detect the substance.