Patents Examined by Jonathan R. Plante
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Patent number: 7594041Abstract: A removable recording medium having an area for storing a content and, when attached to a reproducing apparatus, allowing the content recorded in the area to be reproduced is arranged so as to include, separately from the area for storing the content, an area for storing one or more conditions that allow the content to be reproduced by the reproducing apparatus. With this arrangement, by pre-recording on the recording medium, information for allowing the reproducing apparatus to reproduce a content, the recording apparatus can automatically perform processing such as encoding to a content in accordance with the information recorded on the recording medium and then record the content on the recording medium; and the reproducing apparatus can unconditionally reproduce a content recorded on the recording medium.Type: GrantFiled: November 15, 2002Date of Patent: September 22, 2009Assignee: Sharp Kabushiki KaishaInventors: Tomoko Aono, Kazuto Ohhara, Toshio Nomura, Motohiro Ito, Hiroyuki Katata
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Patent number: 7562163Abstract: A method is disclosed to locate a data storage device disposed in a data storage system. The method selects a target data storage device, identifies a target adapter port in communication with the target data storage device, and determines one or more target addresses, and determines one or more target World Wide Port Names (“WWPNs”). The method selects an enclosure, and a communication pathway disposed in that enclosure, and determines if any storage device ports interconnected with the communication pathway comprise a WWPN that matches any of said target WWPNs. If any storage device ports interconnected with the communication pathway comprise a WWPN that matches any of the target WWPNs, the method then identifies an adapter port in communication with that communication pathway, and determines if that any storage device ports in communication with the identified adapter port have claimed an address that matches a target address.Type: GrantFiled: August 18, 2006Date of Patent: July 14, 2009Assignee: International Business Machines CorporationInventors: Paul Nicholas Cashman, Lokesh Mohan Gupta, Michael John Jones, Kenney Nian Gan Giu
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Patent number: 7539786Abstract: A method for simulating the insertion of a data storage medium into or removal of a data storage medium from an input/output station, alternatively referred to as an import/output station. In one application of the invention, a data storage resides in an I/O station slot. A first variable corresponding to this slot is modified to indicate that the slot is actually empty. A command is issued indicating that the I/O station has been accessed, triggering a scan of the slot by an automated robotic accessor. Since the accessor will detect that the slot is, in fact, full, it will report this status to a library manager which will, in turn, update the first variable. The action of updating this variable is reported to associated devices such as a host computer, host application, or other associated device. In this manner, the operation of the library manager and devices receiving status information may be tested without requiring that a physical data storage medium actually be removed and re-inserted.Type: GrantFiled: August 17, 2005Date of Patent: May 26, 2009Assignee: International Business Machines CorporationInventors: Frank D. Gallo, Jose G. Miranda Gavillan, Khan V. Ngo
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Patent number: 7525533Abstract: An audio communication apparatus including a communication unit configured to communicate with an external device, an input unit configured to input an operating signal for operating the external device; a microphone configured to collect sound, a speaker configured to output sound, and a control unit configured to transmit the sound input from the microphone to the external device via the communication unit and transmit an audio signal received via the communication unit to the speaker, and configured to be connected to the input unit and control enabling and disabling of a function of the input unit.Type: GrantFiled: September 25, 2006Date of Patent: April 28, 2009Assignee: Sony CorporationInventors: Tsuneki Shibuya, Shigeki Mori, Ryo Tokushima, Kazuhiro Sakiyama, Satomi Tanaka, Hiroshi Ito, Reiko Uenaka, Tomonari Murakami
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Patent number: 7512717Abstract: A Fiber Channel (FC) controller shareable by a plurality of operating system domains (OSDs) within a load-store architecture is disclosed. The controller includes a plurality of control/status register (CSR) banks. A respective one of the CSR banks is used by each OSD to request the controller to perform I/O operations with remote FC devices. A load-store bus interface receives from a load-store bus load and store transactions from each OSD. Each transaction includes an OSD identifier identifying the OSD that initiated the transaction. The bus interface directs the transactions to the respective CSR bank based on the OSD identifier. A FC port obtains a distinct FC port identifier for each OSD and transceives FC frames with the remote FC devices using the distinct FC port identifier for each OSD in response to the I/O operation requests. In one embodiment, the controller includes a shared I/O switch coupling the OSDs thereto.Type: GrantFiled: January 27, 2005Date of Patent: March 31, 2009Assignee: Nextio Inc.Inventor: Christopher J. Pettey
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Patent number: 7506218Abstract: An invention is disclosed for a computer software timeout algorithm that reduces the amount of list manipulation needed to satisfy system or network requirements for scheduling and cancelling timeout requests to determine whether the expiration time has been reached for execution of an input/output (I/O) request, thereby requiring action to cancel the I/O operation if it has not yet been completed.Type: GrantFiled: August 18, 2006Date of Patent: March 17, 2009Assignee: International Business Machines CorporationInventors: David Blair Gilgen, William Daniel Wigger
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Patent number: 7496700Abstract: A method and apparatus are disclosed for implementing STP flow control in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. Connections to a SATA HDD are supported using SATA Tunnelling Protocol (STP), which allows SATA traffic to be carried over a SAS network topology. Flow control in a STP connection is applied through a set of special SATA primitives, both for forward and backward flow control. A method is described herein in which STP flow control is supported without the use of a SATA link layer state machine. This allows STP flow control to be terminated on a hop-by-hop basis without knowing the data channel direction or maintaining a SATA link state machine, and while minimizing gate count.Type: GrantFiled: January 6, 2006Date of Patent: February 24, 2009Assignee: PMC-Sierra, Inc.Inventors: Paul Chong, Heng Liao, Cheng Yi
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Patent number: 7493416Abstract: A Fibre Channel controller shareable by a plurality of operating system domains (OSDs) is disclosed. The controller includes a programming interface, located within a system load-store memory map of each OSD by which the OSDs request the controller to perform I/O operations with remote FC devices. The programming interface includes a distinct control/status register (CSR) bank for each of OSD. The OSDs execute load-store instructions addressed to the programming interface to request the I/O operations. Selection logic selects as a target of each of the load-store transactions the distinct CSR bank for the OSD that executed the corresponding load-store instruction. An FC port obtains a distinct FC port identifier for each OSD and transceives FC frames with the remote FC devices using the distinct FC port identifier for each OSD in response to the I/O operation requests. In one embodiment, multiple blade servers share the controller via a shared I/O switch.Type: GrantFiled: January 27, 2005Date of Patent: February 17, 2009Assignee: NextIO Inc.Inventor: Christopher J. Pettey
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Patent number: 7487269Abstract: An apparatus, system, and method are disclosed for grouping connection paths for lock attention data. A grouping request module is included to receive a request to establish a group of connection paths. Each connection path is configured to communicate lock attention data between a host and a control unit. The control unit is configured to control a storage device containing data accessible to a plurality of processes. A connection path selection module is included to select a plurality of connection paths between the host and the control unit and a grouping assignment module configured to assign the plurality of connection paths to a group. In one embodiment, an attention selection module is included to select an attention connection path for communicating lock attention data from any of the connection paths in the group. The attention selection module may select an attention connection path using a load balancing function.Type: GrantFiled: November 18, 2004Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Brian Dow Clark, Juan Alonso Coronado, Beth Ann Peterson
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Patent number: 7480846Abstract: The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder (14) and a second decoder (16), each decoder being able to calculate extrinsic output data from extrinsic input data coming from the other decoder. The decoding circuit according to the invention comprises a single memory (31) for storing the extrinsic data. When a decoder calculates an extrinsic output data from an extrinsic input data coming from the other decoder and stored in the single memory at a certain address, this extrinsic output data is then written at this same address.Type: GrantFiled: May 7, 2003Date of Patent: January 20, 2009Assignee: ST Wireless SAInventors: Sébastien Charpentier, Patrick Valdenaire
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Patent number: 7430502Abstract: Systems, methodologies, media, and other embodiments associated with simulating a processor performance state by controlling a thermal management signal are described. One exemplary system embodiment includes a data structure for storing bit patterns that facilitate controlling a GPIO (General Purpose Input Output) block and addresses of locations to which the bit patterns can be written. The example system may also include a logic configured to receive a request to produce a performance state in a processor and to cause a frequency and voltage to be established in the processor in response to a thermal management signal being generated in response to writing the bit pattern(s) to the address(es).Type: GrantFiled: March 29, 2004Date of Patent: September 30, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventor: Louis B. Hobson
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Patent number: 7404013Abstract: A device communicatively coupled to a host in a Serial Advanced Technology Attachment (SATA) format. The device includes a processor to control operations in the device and a serial interface to control serial communication with the host in accordance with the SATA format. The serial interface, after the transmission of a continued primitive, inserts pass-through information to the host within or outside of a frame information structure (FIS). If the host is not pass-through enabled, the host ignores the pass-through information. However, if the host is pass-through enabled, the host recognizes the pass-through information.Type: GrantFiled: May 17, 2005Date of Patent: July 22, 2008Assignee: Western Digital Technologies, Inc.Inventor: John C. Masiewicz
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Patent number: 7383363Abstract: A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from writing data to a memory until the memory access controller receives a periodic authorization signal to cause the memory access controller to remove the inhibition and write a predetermined amount of data to the memory through a data bus, and 2) releasing the data bus following writing of the predetermined amount of data to the memory by inhibiting the memory access controller from writing further data.Type: GrantFiled: November 19, 2004Date of Patent: June 3, 2008Assignee: Marvell International Technology Ltd.Inventors: Charles Edward Evans, Douglas Gene Keithley
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Patent number: 7376759Abstract: An apparatus and an associated method of operation is provided for performing device communication in accordance with a standard protocol, while enabling deviation from the device communication without termination or corruption of the device communication. The apparatus incorporates a pair of state machines configured to provide standard protocol communication with interrupt capability. A first state machine functions to perform the communication process in accordance with the standard protocol. The first state machine is also configured to deviate from the communication process in order to perform another requested task. A second state machine functions to monitor the communication process being performed by the first state machine. Upon completion of the other requested task by the first state machine, a state of the communication process is provided by the second state machine to enable the communication process to be continued by the first state machine.Type: GrantFiled: February 18, 2004Date of Patent: May 20, 2008Assignee: Adaptec, Inc.Inventor: Ross Stenfort
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Patent number: 7340541Abstract: A system and method for buffering bidirectional digital input/output (I/O) lines. The system (e.g., data acquisition system) may comprise a device including circuitry for buffering bidirectional digital lines. A first integrated circuit (IC) of the device includes a first and a second bidirectional buffer coupled to a first bidirectional digital I/O line, and a second IC of the device includes a third bidirectional buffer. The first IC and the second IC each include a control unit to control the driving direction of the corresponding bidirectional buffers independently to change the direction of the data flow through the first bidirectional digital I/O line from the output direction to the input direction or vice versa. The driving direction of the bidirectional buffers are changed at different times in a particular sequence, and the order depends on whether the direction change is from the output direction to the input direction or vice versa.Type: GrantFiled: September 8, 2004Date of Patent: March 4, 2008Assignee: National Instruments CorporationInventors: Rafael Castro, Andrew B. Moch, Sean M. Nickel
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Patent number: 7333659Abstract: An encoder and an encoding method capable of improving the transfer efficiency in an encoding process is provided. The encoder determines the number of removed bit planes in order that the quantity of generated codes per frame is kept constant when performing the encoding process. A predetermined number of bit planes corresponding to those parts of information that seem relatively small to users are removed. Accordingly, the encoder can prevent variation of processing time in a stage before the encoder performs an encoding process.Type: GrantFiled: April 12, 2004Date of Patent: February 19, 2008Assignee: Sony CorporationInventor: Haruo Togashi
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Patent number: 7296094Abstract: Disclosed is a system using a SAS host controller and SAS expanders to control multiple SATA end devices where the memory contained on the SAS host controller is fixed to ease the cost and power consumption of the SAS host controller device, but where there is an expanded ability to support additional SATA end devices by configuring the allowed native command queue depth to be smaller for each SATA end device, thus allowing more SATA end devices to be supported by a single SAS host controller. An embodiment of the invention has three possible preset configuration states: thirty-two SATA end devices with a native command queue depth of thirty-two; sixty-four SATA end devices with a native command queue depth of sixteen; and one-hundred-twenty-eight SATA end devices with a native command queue depth of eight.Type: GrantFiled: August 20, 2004Date of Patent: November 13, 2007Assignee: LSI CorporationInventors: Patrick R. Bashford, Brian A. Day, Jeffrey M. Rogers
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Patent number: 7254653Abstract: A switch control system has a switch device for selecting a real input device or an emulation input device, an instruction detecting device electrically connected to a computer system and the switch device for detecting signals transmitted to the switch device, and a control device electrically connected to the switch device and the instruction detecting device for receiving a detecting signal from the instruction detecting device and for outputting a control signal to trigger the switch device and to control the selection of the switch device.Type: GrantFiled: August 17, 2004Date of Patent: August 7, 2007Assignee: ICP Electronics Inc.Inventors: Chih-Ming Tsai, Chao-Ren Cheng