Abstract: After O2+ ions are implanted in a silicon substrate (10), heat treatment is applied to the silicon substrate at a temperature of from 1,200° C. to 1,410° C., both inclusive, in an atmosphere having an oxygen content of from 0.1% to 1%, both inclusive, whereby a buried oxide layer (50) is formed. Subsequent to the above heat treatment, post heat treatment may be applied to the silicon substrate (10) at a temperature of from 1,200° C. to 1,410° C., both inclusive, in an atmosphere having an oxygen content of from 1% to 30%, both inclusive. Further, prior to the heat treatment, provisional heat treatment may be applied to the silicon substrate 10 at a temperature of form 350° C. to 1,000° C., both inclusive, for 1 hour or longer.

Abstract: A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors (“FETs”) buried within a single trench. Specifically, two FETs are located at each of two sidewalls of the trench with one FET being disposed above the other FET at each sidewall. Coaxial wiring electrically cross-couples the FETs within the trench such that a pair of cross-coupled inverters comprising the storage flip-flop for the SRAM cell is formed, A fifth, I/O transistor is disposed at the top of the trench structure, and facilitates access to the flip-flop. Specific details of the SRAM trench structure, and fabrication methods therefor are also set forth.

Abstract: A method of making a capacitor over a contact. The method comprises the steps of: (a) depositing an oxide layer over said contact; (b) forming a dual damascene opening in said oxide layer over said contact; (c) depositing a layer of insitu doped polysilicon over said dual damascene opening and said oxide layer; (d) depositing a layer of undoped amorphous polysilicon over said layer of insitu doped polysilicon; (e) removing said layer of undoped amorphous polysilicon and said layer of insitu doped polysilicon that is outside of said dual damascene opening; (f) removing said oxide layer to leave a dual damascene structure comprising insitu doped polysilicon and undoped amorphous polysilicon; (g) forming hemispherical grain (HSG) polysilicon on the surface of said dual damascene structure; (h) forming a dielectric layer over said dual damascene structure; and (i) forming a top electrode over said dielectric layer.

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is converted to an intermetallic layer. A layer of copper intermetallics with halfnium, lanthanum, zirconium or tin, is provided to improve the electromigration resistance and to reduce defect sensitivity. A method is also provided to form a cap atop copper lines, to improve corrosion resistance, which fully covers the surface. Structure and methods are also described to improve the electromigration and corrosion resistance by incorporating carbon atoms in copper intersititial positions.

Abstract: Methods of forming capacitors in memory devices include the steps of forming a first electrically insulating layer having a first conductive contact plug therein, on a semiconductor substrate, and then forming a first diffusion barrier pattern in electrical contact with the first conductive contact plug. A second electrically insulating layer having a contact hole therein is then formed on an upper surface of the first diffusion barrier pattern, to inhibit parasitic oxidation of the first diffusion barrier pattern. A lower electrode of a capacitor is then formed on the second electrically insulating layer. The lower electrode is electrically coupled to the first diffusion barrier pattern and may contact the first diffusion barrier pattern directly or may be coupled through a second diffusion barrier pattern to the first diffusion barrier pattern. A dielectric layer and upper electrode are then formed on the lower electrode.

Abstract: One electrode of a capacitive element is formed by a doped semiconductor film and a non-doped semiconductor film which covers at least part of the doped semiconductor film, and a capacitive dielectric film is formed to cover these semiconductor films. In forming this capacitive dielectric film, enhanced oxidation due to impurities is suppressed, so hardly any native oxide is formed on the surface of one electrode, and a reliable capacitive element having a large capacitance can be manufactured.

Abstract: A densely packed array of vertical semiconductor devices, having pillars with stack capacitors thereon, and methods of making thereof are disclosed. The pillars act as transistor channels, and are formed between upper and lower doped regions. The lower doped regions are self-aligned and are located below the pillars. The array has columns of bitlines and rows of wordlines. The lower doped regions of adjacent bitlines may be isolated from each other without increasing the cell size and allowing a minimum area of approximately 4 F.sup.2 to be maintained. The array is suitable for Gbit DRAM applications because the stack capacitors do not increase array area. The array may have an open bitline, a folded, or an open/folded architecture with dual wordlines, where two transistors are formed on top of each other in each trench. The lower regions may be initially implanted. Alternatively, the lower regions may be diffused below the pillars after forming thereof.

Abstract: A tubular reaction chamber is mounted on an annular insulating plate disposed on a grounded metallic base plate. A cylindrical outer electrode connected to a high-frequency power supply is disposed around said tubular reaction chamber, and a cylindrical inner electrode is disposed in said reaction chamber coaxially with said cylindrical outer electrode. The cylindrical inner electrode has a plurality of inlet holes defined therein, and a lower end disposed in an opening defined in the metallic base plate and fixed to said metallic base plate. A holder is disposed in said cylindrical inner electrode for supporting a plurality of wafers at spaced intervals.

Abstract: A method for forming a bottom polysilicon electrode of a stacked capacitor for DRAMs makes use of a double-layered polysilicon structure and a phosphoric acid etching. When the double-layered polysilicon structure is etched with the phosphoric acid, the polysilicon grain boundary is etched at a rate faster than the polysilicon grain itself so as to enable the formation of a rugged surface and thus increases the total surface area.

Abstract: A method of fabricating a semiconductor device is provided wherein a first semiconductor substrate is prepared with a first insulating film formed over a first main surface of the first semiconductor substrate, s semiconductor film of n-type conductivity formed over the first insulating film, and a second insulating film formed over the semiconductor film so as to cover the first main surface. A second semiconductor substrate is also prepared with a third insulating film formed over the second semiconductor substrate. Next, the second insulating film and third insulating films are bonded together by thermal processing to join the first semiconductor substrate and the second semiconductor substrate. A portion of a second main surface of said first semiconductor substrate, opposite to said first main surface of the first semiconductor substrate is then removed to expose a portion of the first semiconductor substrate, thereby providing a semiconductor layer.

Abstract: In a semiconductor device manufacturing method, a first insulating film is formed on a semiconductor substrate. A contact hole is selectively formed in the first insulating film. A first conductive film is formed on the first insulating film to fill the interior of the contact hole. A second insulating film is formed on the first conductive film. A second conductive film is formed on the second insulating film. The second insulating film and the second conductive film are patterned to leave the second insulating film and the second conductive film only immediately above the contact hole. A third conductive film is formed on the surfaces of the first conductive film, the second insulating film, and the second conductive film. The third conductive film on the first and second conductive films is removed to form a cylindrical lower electrode consisting of the third conductive film left only on the side surfaces of the second insulating film and the second conductive film.

Abstract: This invention relates to a method for improving the chemical and electrical performance characteristics of a high dielectric constant material. The method comprises the steps of first obtaining a barium containing high dielectric constant material, the material having an upper surface and then modifying the surface chemistry of said upper surface by interacting said upper surface with a gas reactant in a closed environment. In a variant of the method, the gas reactant preferentially reacting with upper surface as compared to the bulk.

Abstract: A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs at a late stage in the manufacture of the ROM. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N.sup.+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped N-type, gate electrodes are defined by photolithography, and then self-aligned silicide layers are formed on the gate electrodes. An insulating layer is then formed over the gate electrodes. Programming of the ROM is accomplished by forming a mask on the insulating layer and then implanting ions through openings in the mask, through the insulating layer and the silicide layer, and into the polysilicon layer.

Abstract: A miniature electrostatic capacitive sensor in which electrical insulation is reliably established between a CV conversion circuit and a sensing unit. Also disclosed is a manufacturing method for the above type of capacitive sensor. The capacitive sensor is constructed of a sensing unit having a movable electrode and a stationary electrode, and a CV-conversion-circuit-forming portion having a CV conversion circuit. The movable electrode is constructed of a first support portion, a leaf spring connected to the first support portion, and a mass portion movably supported by the leaf spring. The stationary electrode is formed of a second support portion and a projecting portion connected to the second support portion. The CV-conversion-circuit forming portion and the first and second support portion are made thin. Accordingly, a shallow clearance is formed between the CV-conversion-circuit forming portion and each of the first support portion and the stationary electrode.

Abstract: A memory integrated circuit which is driven with a low power and reduced the cell area and a method for manufacturing the same. A plurality of active regions having an H-shape with four source regions and common drain region are formed on a semiconductor substrate. Four word lines each having a different source correspondingly pass through each of the four source regions of an active region, thereby forming four transistors driven, independently. These four transistors are designed so as to share one bit line, thereby reducing the driving voltage of the transistor to 1/4 Vcc. With a low power driving source, four transistors and a capacitor are formed on a small area to thereby reduce the cell size to 33% and even more.

Abstract: A ferroelectric capacitor taking a multilayer structure wherein a conductive oxide layer which is formed between a metal electrode and a ferroelectric layer, capable of enhancing the fatigue behavior in addition to reducing the leakage current. The multilayer structure can be fabricated by depositing a silicon oxide (SiO.sub.2) layer, an adhesive layer, a bottom metal layer, a lower conductive oxide layer, a ferroelectric layer, an upper conductive oxide layer and a top metal electrode layer are deposited over a silicon substrate, in sequence.

Abstract: A semiconductor device having an active layer comprising crystalline silicon, said active layer comprising a first layer comprising crystalline silicon formed on an insulating surface and a second layer comprising crystalline silicon formed on said first layer, wherein said first layer contains a metal element at a first concentration while said second layer is free from said metal element or contains said metal element at a second concentration which is lower than said first concentration.

Abstract: Method for fabricating a compound semiconductor device including the steps of forming an active layer on a substrate, forming a plurality of ohmic electrodes on predetermined regions of the active layer, forming a mask material layer on the entire surface of the active layer inclusive of the ohmic electrodes, removing the mask material layer from predetermined regions thereof to open regions of the active layer between the ohmic electrodes and at least any one of the ohmic electrodes, etching the opened regions of the active layer each to a predetermined depth, and removing the mask material layer and forming a gate electrode on each of the opened regions of the active layer each having been etched to the predetermined depth, whereby the possibility of forming devices having threshold voltages different from one another on the same substrate allows application of the device of the present invention to variety of MMIC.

Abstract: A method of post-processing a solid-state imaging device including a wafer processing step 1 (S1), an assembly step 2 (S2) in which packaging is performed, an inspection step 3 (S3), and an annealing step (S4) in which a solid-state having gone through the inspection step 3 is annealed at a predetermined temperature. The method makes it possible to reduce the level of an image defect that occurs after assembly.

Abstract: According to the present invention, there is provided a means which can prevent a formation failure of hemispherical silicon crystal grains of DRAM having a stacked capacitor structure having the hemispherical silicon crystal grains, can introduce a sufficient amount of an impurity into the hemispherical silicon crystal grains, and can prevent capacity deterioration by depletion. In the present invention, a first silicon film is formed on a semiconductor substrate incorporated with an MOS transistor and then worked into a predetermined shape, and a spontaneous oxide layer is then formed on the surface of the first silicon film. In succession, a second silicon film containing the impurity and a third silicon film containing no impurity are formed, and annealing is then done without exposing it to the atmosphere to form the hemispherical silicon crystal grains.