Abstract: A method of processing image data that includes identifying picture elements of a first image portion having a first hue and a first saturation assigned to the first hue, the first hue lying in a first critical hue interval, identifying picture elements a second image portion having a second hue and a second saturation assigned to the second hue, the second hue lying in a second critical hue interval, and changing the first saturation by an amount delta S, at least one of the first and the second hues not being changed, and the delta S varying for picture elements lying in the first image portion.

Abstract: In an embodiment, a method of processing memory requests in a first processing device is provided. The method includes generating a memory request associated with a memory address located in an unpinned memory space managed by an operating system running on a second processing device; and responsive to a determination that the memory address is not resident in a physical memory, transmitting a message to the second processing device. In response to the message, the operating system controls the second processing device to bring the memory address into the physical memory.

Abstract: Disclosed is a graphic display apparatus including a display unit, a reference object length storage unit in which specified parts of reference objects and actual lengths of the specified parts are stored, an image storage unit in which images are stored, an image display control unit which displays a specified image which is specified based on a user's operation in the display unit, a specified image part setting unit which detects a specified part of a reference object in the specified image and sets the detected specified part as a specified image part, a coordinate system setting unit which superimposes a coordinate system on the specified image and sets a display range of the coordinate system based on an actual length of the specified image part, and a graphic display control unit which superimposes and displays a graphic on the specified image.

Abstract: Aspects of the disclosure relate to a method of controlling a graphics processing unit. In an example, the method includes receiving one or more tasks from a host processor, and scheduling, independently from the host processor, the one or more tasks to be selectively executed by a shader processor and one or more fixed function hardware units, wherein the shader processor is configured to execute a plurality of instructions in parallel, and the one or more fixed function hardware units are configured to render graphics data.

Abstract: A method, processing system, and/or computer program product for generating a graphic for application to a surface to produce a plaque. In one aspect, the method includes, in a processing system: receiving, from a user, first location data indicative of a first location; receiving, from the user, second location data indicative of a plurality of second locations; determining for each second location, a displacement pair, each displacement pair being indicative of: a distance between the first location and the respective second location; and a direction of the respective second location relative to the first location; and generating, using each displacement pair, graphical data indicative of a graphic for application to a surface, wherein the graphical data is indicative of the distance and direction of each second location relative to the first location.

Abstract: An image displaying device with an image cache data storage unit, including: an image cache identifier generating unit that obtains a hash value of a fixed length from sampling data of original image data and generates an image cache identifier unique to said original image data based on the hash value of a fixed length; an image cache searching unit that checks whether image cache data to which the generated image cache identifier is added is stored in said image cache memory or not; and an image cache generating unit that, when the image cache data has been not stored in said image cache memory, generates image cache data by adding the image cache identifier generated by said image cache identifier generating unit to the original image data and stores the image cache data in said image cache memory.

Abstract: Methods and systems relating to providing constants are provided. In an embodiment, a method of providing constants in a processing device includes copying a constant of a first constant buffer to a second constant buffer, the first and second constant buffers being included in a ring of constant buffers and a size of the ring being one greater than a number of processes that the processing device can process concurrently, updating a value of the constant in the second buffer, and binding a command to be executed on the processing device to the second constant buffer.

Abstract: Methods, systems, and machine readable tangible storage media that can provide for smooth and seamless opening of a file from, for example, a preview are described. A preview of a file can be generated by a non-native viewer or reader application and in response to a command to open a file in a native application, the preview can continue to be displayed while the native application launches such that a user will perceive no interruption in display of the content. The non-native application can pass a display state (e.g. a page number or scroll position) to the native application such that the native application continues to show a user's current position or view port into the file.

Abstract: Virtualization of graphics resources and thread blocking is disclosed. In one exemplary embodiment, a system and method of a kernel in an operating system including generating a data structure having an identifier of a graphics resource assigned to a physical memory location in video memory, and blocking access to the physical memory location if a data within the physical memory location is in transition between video memory and system memory wherein a client application accesses memory in the system memory directly and accesses memory in the video memory through a virtual memory map.

Abstract: A method and apparatus for sorting data into spatial bins or buckets using a graphics processing unit (GPU). The method takes unsorted point data as input and scatters the points, in sorted order, into a set of bins. This key operation enables construction of a spatial data structure that is useful for applications such as particle simulation or collision detection. The disclosed method achieves better performance scaling than previous methods by exploiting geometry shaders to progressively trim the size of a working set. The method also leverages predicated rendering functionality to allow early termination without CPU/GPU synchronization. Furthermore, unlike previous techniques, the method can guarantee sorted output without requiring sorted input. This allows the method to be used to implement a form of bucket sort using the GPU.

Abstract: A display system comprises line buffer memory that stores input image data in a first color space, and a plurality of gamut mapping modules that accept the input image data from the line buffer memory and performs a gamut mapping operation to produce mapped image data specified in a second color space. The system also includes a subpixel rendering module that renders the image data specified in the second color space for display on a display panel substantially comprised of a particular subpixel repeating group. The system architecture utilizes a plurality of gamut mapping modules which in turn allows for a reduction in the size of line buffer memory needed for the subpixel rendering operation.

Abstract: Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.

Abstract: Systems and methods for customizing behavior of a computing system based on details of interactions with the computing system by a user, such as a direction, intensity, or magnitude of a particular input from a user input device.

Abstract: Methods and systems for processing video data are disclosed herein and may include determining a first video format associated with video data to be displayed on a first video display communicatively coupled to a single mobile multiple media processor that supports a plurality of display formats. The single mobile multiple media processor may be integrated within a mobile device. An amount of the video data that is transferred from memory to the first video display, by a DMA controller, may be restricted based on the determined first video format associated with the video data to be displayed on a first video display. Only the restricted amount of the video data that is to be displayed by the first video display may be transferred from the memory to the first video display by the DMA controller.

Abstract: A method and system for coordinated data execution in a computer system. The system includes a first graphics processor coupled to a first memory and a second graphics processor coupled to a second memory. A graphics bus is configured to couple the first graphics processor and the second graphics processor. The first graphics processor and the second graphics processor are configured for coordinated data execution via communication across the graphics bus.

Abstract: A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and facilitates power conservation by utilizing a single unified data fetch stage (e.g., unified data fetch module) that retrieves a variety of different pixel surface attribute values (e.g., depth, color, and/or texture values) in a single stage. Different types of pixel surface attribute data (e.g., depth, color, texture) associated with multiple graphics processing functions (e.g., color blending, texture mapping, etc.) are retrieved in the single unified data fetch graphics pipeline stage. The pixel surface attribute values may be placed in corresponding variable fields of a pixel packet row. The pixel packet rows including the pixel surface attribute values are forwarded to downstream graphics pipeline stages (e.g., an arithmetic logic pipestage).

Abstract: A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and also facilitates power conservation. Pixel packet information includes pixel surface attribute values are retrieved in a single unified data fetch stage. At a data fetch pipestage a determination may be made if the pixel packet information contributes to an image display presentation (e.g., a depth comparison of Z values is performed determine if the pixel is occluded). A pixel packet status indicator (e.g., a kill bit) is set in the sideband portion of a pixel packet and the pixel packet is forwarded for processing in accordance with the pixel packet status indicator.

Abstract: A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and facilitates power conservation by utilizing a single unified data fetch stage (e.g., unified data fetch module) that retrieves a variety of different pixel surface attribute values for different attribute types (e.g., depth, color, and/or texture values) in a single stage. Different types of pixel surface attribute data (e.g., depth, color, texture) associated with multiple graphics processing functions (e.g., color blending, texture mapping, etc.) are retrieved in the single unified data fetch graphics pipeline stage. The pixel packet rows including the pixel surface attribute values are forwarded to other graphics pipeline stages for single thread processing (e.g. to a universal arithmetic logic unit capable of performing multiple graphics functions on the pixel surface attribute values).

Abstract: An in-vehicle obstacle information notification apparatus for displaying an intersection map on a screen of a display section and superimposing a movable body mark on the intersection map when an own vehicle is in an intersection-surrounding area is disclosed. The display section displays the intersection map in a first mode or a second mode. In the first mode, an upper direction of the map is fixed to a given direction, which is determined before the entry into the intersection. In the second mode, the upper direction of the map on the screen is determined based on own vehicle direction, which is changed at a turn at the intersection. Based on information on a movable body in the intersection-surrounding area, the in-vehicle obstacle information notification apparatus determines whether to set the first mode or the second mode as a display mode of the display section.

Abstract: A multi-graphics processor system includes a CPU; a first GPU connected to the CPU via an input/output interface; and a second GPU connected to the first GPU via a second-GPU interface. The first GPU is provided with a second-GPU bus for communicating the CPU and the second GPU via the second-GPU interface. The CPU communicates with the second GPU via the second-GPU bus after receiving a signal indicating the timing of the data communication.