Patents Examined by Jordon Klein
  • Patent number: 7820509
    Abstract: The method of manufacturing a semiconductor device, including a first region where a transistor including a gate electrode of a stacked structure is formed, a second region where a transistor including a gate electrode of a single-layer structure is formed, and a third region positioned in a boundary part between the first region and the second region, includes: depositing a first conductive film, patterning the first conductive film in the first region and the third region so that the outer edge is positioned in the third region, depositing the second conductive film, patterning the second conductive film to form a control gate in the first region while leaving the second conductive film, covering the second region and having the inner edge positioned inner of the outer edge of the first conductive film, and patterning the second conductive film in the second region to form the gate electrode.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: October 26, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Ogawa, Hideyuki Kojima, Taiji Ema