Abstract: A DRAM capacitor and a method for fabricating the same are disclosed. The method sequentially formed word lines, landing pads, first interpoly dielectric (IPD1)layer, bit line, and IPD2 layer, and then in terms of line masks, nitride cap nitride spacer and landing pad to serve as etching mask or stopping layer, and avoid the usage of a mask layer of storage node contact. Furthermore, the invention fully utilizes the etching selectively between IPD2 (BPSG) layer and IPD1 layer (densified TEOS) by an anhydrous HF to expand the space in an etched IPD2 layer to increase the capacitor area.