Patents Examined by Jose R. Diaz
  • Patent number: 10672941
    Abstract: A method (200) for fabricating thin-film optoelectronic devices (100), the method comprising: providing a substrate (110), forming a back-contact layer (120); forming at least one absorber layer (130) made of an ABC chalcogenide material, adding at least one alkali metal (235), and forming at least one cavity (236, 610, 612, 613) at the surface of the absorber layer wherein forming of said at least one cavity is by dissolving away from said surface of the absorber layer at least one crystal aggregate comprising at least one alkali crystal comprising at least one alkali metal. The method (200) is advantageous for more environmentally-friendly production of photovoltaic devices (100) on flexible substrates with high photovoltaic conversion efficiency and faster production rate.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: June 2, 2020
    Assignees: FLISOM AG, EMPA
    Inventors: Patrick Reinhard, Fabian Pianezzi, Benjamin Bissig, Stephan Buecheler, Ayodhya Nath Tiwari
  • Patent number: 10672901
    Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 2, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Christopher Boguslaw Kocon, Seetharaman Sridhar, Satoshi Suzuki, Simon John Molloy
  • Patent number: 10672870
    Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure has a channel region and a source/drain region. A gate structure is formed over the channel region of the fin structure. A first source/drain etching is performed to recess the source/drain region of the fin structure. After the first source/drain etching, a second source/drain etching is performed to further recess the source/drain region of the fin structure. After the second source/drain etching, a third source/drain etching is performed to further recess the source/drain region of the fin structure, thereby forming a source/drain recess. One or more epitaxial layers are formed in the source/drain recess. The first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung Chen, Kang-Min Kuo, Long-Jie Hong
  • Patent number: 10672752
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 10672719
    Abstract: A semiconductor package includes a wiring portion including an insulating layer, conductive patterns disposed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns, a semiconductor chip disposed on the wiring portion, an encapsulant disposed on the wiring portion and encapsulating at least a portion of the semiconductor chip, and a metal layer disposed on the semiconductor chip and the encapsulant and having a thickness of 10 ?m to 70 ?m.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kang Heon Hur, Jong Man Kim, Kyung Ho Lee, Han Kim
  • Patent number: 10665604
    Abstract: An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: May 26, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Tatsunori Inoue
  • Patent number: 10656479
    Abstract: In an IPS-mode liquid crystal display device, the area of a terminal portion is decreased. A liquid crystal display device includes a TFT substrate and a counter substrate attached to the TFT substrate with a sealing material, and includes a display region and a terminal portion formed on the TFT substrate. A shielding transparent conductive film is formed on the outer side of the counter substrate. On the terminal portion, an earth pad formed with a transparent conductive film is formed on an organic passivation film. The shielding transparent conductive film is connected to the earth pad through a conductor. Below organic passivation film of the terminal portion, a wire is formed.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: May 19, 2020
    Assignee: Japan Display Inc.
    Inventors: Hiroyuki Abe, Kentaro Agata, Masaki Murase, Kazune Matsumura
  • Patent number: 10651109
    Abstract: A method of forming a semiconductor device includes providing a semiconductor package comprising an electrically insulating mold compound body, a semiconductor die that is encapsulated by the mold compound body, a plurality of electrically conductive leads that each protrude out of the mold compound body, and a metal heat slug, the metal heat slug comprising a rear surface that is exposed from the mold compound body, coating outer portions of the leads that are exposed from the mold compound body with a metal coating, and after completing the coating of the outer portions of the leads, providing a planar metallic heat sink interface surface on the semiconductor device which is exposed from the mold compound body, and substantially devoid of the metal coating.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 12, 2020
    Assignee: Infineon Technologies AG
    Inventors: Syahir Abd Hamid, Jagen Krishnan, Mian Mian Lam, Jayaganasan Narayanasamy, Fabian Schnoy, Thomas Stoek, Christian Stuempfl
  • Patent number: 10644203
    Abstract: A light emitting element includes a semiconductor structure including a first layer including a first and a second regions, and a second layer above the second region, the first region including extending portions each extending into the second region from an outer peripheral region; a first insulating layer including first through-holes respectively located on the extending portions, and a second through-hole located above the second region; a second insulating layer including a third and a fourth through-holes; a first external electrode connected with the first layer via the first through-holes; and a second external electrode connected with the second layer via the second through-hole. The extending portions are each located in an area, on a top surface of the first layer, other than an area overlapping any of corner portions of the first external electrode and other than an area overlapping any of corner portions of the second external electrode.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: May 5, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Akihiro Nakamura, Keiji Emura
  • Patent number: 10644190
    Abstract: A fluidic assembly method is provided that uses a counterbore pocket structure. The method is based upon the use of a substrate with a plurality of counterbore pocket structures formed in the top surface, with each counterbore pocket structure having a through-hole to the substrate bottom surface. The method flows an ink with a plurality of objects over the substrate top surface. As noted above, the objects may be micro-objects in the shape of a disk. For example, the substrate may be a transparent substrate and the disks may be light emitting diode (LED) disks. Simultaneously, a suction pressure is created at the substrate bottom surface. In response to the suction pressure from the through-holes, the objects are drawn into the counterbore pocket structures. Also provided is a related fluidic substrate assembly.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: May 5, 2020
    Assignee: eLux Inc.
    Inventors: Changqing Zhan, Paul John Schuele, Mark Albert Crowder, Sean Mathew Garner, Timothy James Kiczenski
  • Patent number: 10643971
    Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: May 5, 2020
    Assignee: Intel Deutschland GMBH
    Inventors: Gottfried Beer, Irmgard Escher-Poeppel
  • Patent number: 10644017
    Abstract: On the upper surface of a fin projecting from the upper surface of a semiconductor substrate, there are formed a control gate electrode through a gate insulating film and a memory gate electrode through a gate insulating film. A semiconductor region is formed in the fin beside the control gate electrode. On the semiconductor region, an insulating film, a first interlayer insulating film, and a second interlayer insulating film are formed. A plug reaching the semiconductor region is formed in the second interlayer insulating film, the first interlayer insulating film, and the insulating film. A cap film is formed between the control gate electrode and the interlayer insulating film, and the plug is positioned also right above the cap film.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomohiro Yamashita
  • Patent number: 10636713
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Patent number: 10629519
    Abstract: A semiconductor device package includes an electronic device, a conductive frame and a first molding layer. The conductive frame is disposed over and electrically connected to the electronic device, and the conductive frame includes a plurality of leads. The first molding layer covers the electronic device and a portion of the conductive frame, and is disposed between at least two adjacent ones of the leads.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 21, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu
  • Patent number: 10629634
    Abstract: A pixel array substrate includes signal lines arranged in an arranging direction, pixel structures electrically connected to the signal lines, a driving element and fan-out traces. Each of the fan-out traces is electrically connected to one of the signal lines and the driving element. A fan-out trace group includes a first fan-out trace and a second fan-out trace. A main portion of the first fan-out trace extends in a first direction, and the first direction and the arranging direction have a first angle ? therebetween. A main portion of the second fan-out trace extends in a second direction, and the second direction and the arranging direction have a second angle ? therebetween. The first angle ? is different from the second angle ?. In addition, another pixel array substrate has also been proposed.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: April 21, 2020
    Assignee: Au Optronics Corporation
    Inventor: Bo-Xuan Liao
  • Patent number: 10629624
    Abstract: A thin film transistor array panel includes a substrate, a gate insulating layer, an interface layer, and a semiconductor layer. The gate insulating layer is disposed on the substrate. The interface layer is disposed on the gate insulating layer. The semiconductor layer is disposed on the interface layer. The interface layer includes a fluorinated silicon oxide. The semiconductor layer includes a p-type oxide semiconductor material.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: April 21, 2020
    Assignees: SAMSUNG DISPLAY CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jae Heung Ha, Jong Woo Kim, Ji Young Moon, Min Ho Oh, Seung Jae Lee, Yoon Hyeung Cho, Young Cheol Joo, Hyeong Joon Kim, Eun-Kil Park, Sang Jin Han
  • Patent number: 10629782
    Abstract: A light emitting device package may include: a light emitting structure including a plurality of light emitting regions configured to emit light, respectively; a plurality of light adjusting layers formed above the light emitting regions to change characteristics of the light emitted from the light emitting regions, respectively; a plurality of electrodes configured to control the light emitting regions to emit the light, respectively; and an isolation insulating layer disposed between the light emitting regions to insulate the light emitting regions from one another, the isolation insulating layer forming a continuous structure with respect to the light emitting regions.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Il Kim, Hyong Sik Won, Wan Tae Lim, Nam Goo Cha
  • Patent number: 10629535
    Abstract: An integrated circuit is provided that comprises a first ground plane associated with a first set of circuits that have a first operational temperature requirement, and a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement. The second ground plane is substantially thermally isolated from the first ground plane. A superconducting coupler electrically couples the first ground plane and the second ground plane while maintaining relative thermal isolation between the first ground plane and the second ground plane.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 21, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Patrick Alan Loney, Aaron Ashley Hathaway, Daniel Robert Queen, John X. Przybysz, Robert Miles Young
  • Patent number: 10622357
    Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 14, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., STMICROELECTRONICS, INC.
    Inventors: Xiuyu Cai, Qing Liu, Ruilong Xie, Chun-Chen Yeh
  • Patent number: 10622280
    Abstract: A semiconductor device includes a semiconductor element, a cooler, and a heat conductive body. The cooler faces one surface of the semiconductor element, and has a flow passage of a coolant. As viewed from the flow direction of the coolant, a width of the flow passage is wider than a width of the semiconductor element. The heat conductive body is made from graphite having such an anisotropy that a heat conductivity in the in-plane direction of a predetermined surface is higher than a heat conductivity in the normal direction of the predetermined surface. The width of the heat conductive body is wider than the width of the semiconductor element as viewed from the flow direction of the coolant. The heat conductive body is configured such that the predetermined surface is non-parallel to both of the flow direction of the coolant and the one surface of the semiconductor element.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: April 14, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masataka Deguchi