Patents Examined by Jose R. Diaz
  • Patent number: 11081575
    Abstract: An insulated gate bipolar transistor (IGBT) device and a method for manufacturing the same are provided. The present disclosure relates to power semiconductor devices. In order to relieve the problem of wafer warping caused by trench stress in an IGBT manufacturing process without affecting other performance parameters of the IGBT, it provides the following technical solution: optimizing the design of arrangement densities and arrangement regions of device trenches. The present disclosure can alleviate the problem of wafer warping caused by trench stress in the IGBT manufacturing process, improve the product yield of IGBT chips, and enhance the latch-up immunity of the IGBT, so that the IGBT is more robust and durable.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 3, 2021
    Assignee: ZHONG SHAN HONSON ELECTRONIC TECHNOLOGIES LIMITED
    Inventors: Johnny Kin On Sin, Hao Feng, Song Yuan
  • Patent number: 11081446
    Abstract: A semiconductor device that includes active patterns defined in a substrate, and gate patterns extending in a first direction while traversing the active patterns. First wiring line patterns disposed over a first dielectric layer which covers the gate patterns, and extending in the first direction. The first wiring line patterns comprise internal wiring line patterns coupled with first vertical vias, which pass through the first dielectric layer and are coupled to the active patterns and the gate patterns, and power routing patterns not coupled with the first vertical vias. The first wiring line patterns are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting with the first direction, and the first active patterns are disposed between the power routing patterns when viewed on a top.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: August 3, 2021
    Assignee: SK hynix Inc.
    Inventors: Nam-Hea Jang, Young-Hoon Kim
  • Patent number: 11081678
    Abstract: A display panel, a method for fabricating the same, and a display device are disclosed, where the display panel includes: a base substrate, sub-pixel units in at least two colors on the base substrate, and an anti-reflection layer on a side of the sub-pixel units away from the base substrate, wherein the anti-reflection layer includes anti-reflection components arranged in an array, which correspond to the sub-pixel units in a one-to-one manner, and are configured to alleviate reflected light in the same colors as the corresponding sub-pixel units, and sub-pixel units in different colors correspond to different anti-reflection components.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: August 3, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Wenfeng Song
  • Patent number: 11075161
    Abstract: An interconnect structure is provided. The interconnect structure includes a first metallization layer, an insulating layer and a second metallization layer. The first metallization layer includes, at an uppermost surface thereof, a first body formed of first dielectric material, first metallic elements and buffer elements formed of second dielectric material adjacent the first metallic elements. The insulating layer is disposed on the uppermost surface of the first metallization layer and defines apertures located at the first metallic elements and the corresponding buffer elements. The second metallization layer is disposed on the insulating layer and includes a second body formed of first dielectric material and second metallic elements located at the apertures and extending through the apertures to contact the corresponding first metallic elements and the corresponding buffer elements.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann Mignot, Hsueh-Chung Chen, Junli Wang, Chi-Chun Liu, Mary Claire Silvestre
  • Patent number: 11069673
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 11056661
    Abstract: The present invention provides a color conversion layer, a manufacturing method of the color conversion layer, and a display panel. The color conversion layer is used in a display panel having a direct surface light source. The color conversion layer includes a quantum dot film and a functional film. The functional film is arranged at one side of the quantum dot film facing the direct surface light source. A light wave emitted by the direct surface light source is transmitted through the functional film into the quantum dot film. A light wave excited by the quantum dot film is reflected into the quantum dot film through the functional film.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: July 6, 2021
    Inventors: Guiyang Zhang, Guowei Zha
  • Patent number: 11049769
    Abstract: Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Antonino Rigano, Roberto Somaschini
  • Patent number: 11050039
    Abstract: Disclosed are an organic light emitting display device and a method for manufacturing a cover window thereof. The organic light emitting display device includes a display panel configured to display an image, and a cover window located above the display panel. The cover window includes a light path control structure configured to adjust a range of visibility of the image displayed by the display panel and to prevent occurrence of ghost mura.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: June 29, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jin-Woo Hong, Wan-Seop Kim
  • Patent number: 11043584
    Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer and a recess. The group III-V body layer is disposed on the substrate. The group III-V barrier layer is disposed on the group III-V body layer in the active region and the isolation region. The recess is disposed in the group III-V barrier layer in the active region.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: June 22, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Wen-Jung Liao
  • Patent number: 11043419
    Abstract: A semiconductor device according to an embodiment comprises a semiconductor substrate having a through hole from a first face to a second face on an opposite side to the first face. A metal part is provided inside the through hole. A stacked film is provided between the metal part and an inner side surface of the through hole, and comprises a plurality of different material films of two or more types having a relative permittivity equal to or lower than 6.5.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: June 22, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Ippei Kume
  • Patent number: 11037985
    Abstract: A semiconductor device includes a first electrode and a first carbon layer on the first electrode. A switch layer is disposed on the first carbon layer and a second carbon layer is disposed on the switch layer. At least one tunneling oxide layer is disposed between the first carbon layer and the second carbon layer. The device further includes a second electrode on the second carbon layer.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Jun Seong, Jun Hwan Paik, Hyung Jong Jeong
  • Patent number: 11038029
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Wen Tsau, Chun-I Wu, Ziwei Fang, Huang-Lin Chao, I-Ming Chang, Chung-Liang Cheng, Chih-Cheng Lin
  • Patent number: 11031433
    Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: June 8, 2021
    Assignee: STMicroelectronics (Crolles) SAS
    Inventors: Frederic Lalanne, Laurent Gay, Pascal Fonteneau, Yann Henrion, Francois Guyader
  • Patent number: 11018113
    Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lipu Kris Chuang, Chung-Hao Tsai, Hsin-Yu Pan, Yi-Che Chiang, Chien-Chang Lin
  • Patent number: 11018224
    Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ta Yu, Sheng-Chen Wang, Wei-Yuan Lu, Chien-I Kuo, Li-Li Su, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
  • Patent number: 11011485
    Abstract: A semiconductor package includes: a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and the connection structure including an insulating layer having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the via hole are connected to have a stepped portion.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hoon Choi, Doo Hwan Lee, Joo Young Choi, Sung Han, Byung Ho Kim
  • Patent number: 11011575
    Abstract: A circuit selector of embedded magnetoresistive random access memory (EMRAM) includes a transistor comprising a source/drain terminal coupled to a first magnetic tunneling junction (MTJ) and a second MTJ, a gate terminal, and a drain/source terminal coupled to a voltage source. Preferably, the first MTJ includes a first free layer, a first barrier layer, and a first pinned layer, in which the first free layer is coupled to the source/drain terminal and the first pinned layer is coupled to a first circuit. The second MTJ includes a second free layer, a second barrier layer, and a second pinned layer, in which the second pinned layer is coupled to the source/drain terminal and the second free layer is coupled to a second circuit.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: May 18, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Sheng Feng, Yu-Chun Chen, Chiu-Jung Chiu
  • Patent number: 11011456
    Abstract: A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 18, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thai Kee Gan, Lee Shuang Wang, Jo Ean Joanna Chye
  • Patent number: 11004807
    Abstract: A method of manufacturing a laminated substrate including an insulation substrate comprised of ceramic, and a front electrode formed on a front surface of the insulation substrate, a semiconductor element being mountable on a front surface of the front electrode, including forming the front electrode on the front surface of the insulation substrate, and before or after the forming the front electrode, applying laser processing to the front surface of the insulation substrate at an outer peripheral area of the front electrode to modify a conductive property of the front surface of the insulation substrate to have electrical conductivity.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: May 11, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keisuke Yamashiro
  • Patent number: 10998263
    Abstract: An IC device, such as a wafer, chip, die, processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like include a chamfered VIA that connects an upper wiring line and a first lower wiring line. The chamfered VIA includes a chamfer or fillet upon the edge that connects the VIA sidewall(s) with the VIA contact surface that is connected to the first lower wiring line. The chamfer or fillet effectively increases the amount of a dielectric material, such as a high-k dielectric material, within a trench of the VIA and that is between the chamfered VIA and a second lower wiring line that neighbors the first lower wiring line. This increased dielectric material improves TDDB between the chamfered VIA and the second lower wiring line and mitigates TDDB effects, such as electrical shorts between the chamfered VIA and the second lower wiring line.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jim Shih-Chun Liang, Naftali E. Lustig, Baozhen Li, Ning Lu