Abstract: The present invention provides a display method realizing reduction in a moving picture blurring by forming one frame by two fields of different luminance, in which increase in an unapplied voltage due to shortening of data voltage write time is suppressed. A gate voltage is applied in a light field for a period of time which is twice as long as scan line selection time, thereby decreasing an unapplied voltage. On the other hand, a gate voltage is applied normally in a dark field for the scan line selection time, so that the case where the unapplied voltage increases is eliminated. As a result, an image with high reproducibility can be obtained.

Abstract: An image processing unit (2 in FIG. 1) discards a high gray level side of input image data (RiGiBi) in accordance with a chroma coefficient (Csc), thereby to generate a signal of lowered chroma, and it expands the signal into output image data (RoGoBo) of full scale. Besides, the image processing unit (2) generates an image adjustment parameter (Th) and performs a control so as to reduce power of backlight (6), in interlocking with the full-scale expansion.

Abstract: An integrated circuit device includes: a data line driving circuit provided for each of a plurality of data signal supply lines that supplies a multiplexed data signal to a corresponding data signal supply line; an order offset register that stores a first order offset setting value; an order setting circuit that sets the order of driving the first pixel; and an order offset addition circuit corresponding to the data line driving circuit. When the data line driving circuit drives the q-th (q is a natural number less than p) pixel in the r-th (r is a natural number less than p) place in the order, the order offset addition circuit processes addition of an order offset correction value based on the r-th order offset setting value among the first order offset setting value.

Abstract: A gate driver including a shift register, a level shifter, an output buffer, and a processing unit. The shift register generates a shifted signal. The level shifter generates a level signal according to a first operation voltage, a second operation voltage and the shifted signal. The output buffer provides a scan signal according to the level signal. The processing unit controls the level signal to follow the second operation voltage when the first operation voltage equals to a first preset value and the second operation voltage is higher than a second preset value less than the first preset value.

Abstract: A dot-matrix display data refresh charging/discharging control method and system is proposed, which is designed for integration to a dot-matrix display device for providing a data refresh charging/discharging control mechanism on the dot-matrix display device. The proposed method and system is characterized by the capability of prior to a data refresh action on each pixel, switching the pixel for connection to a voltage-neutralizing point for the purpose of neutralizing the current data voltage charge on the pixel to substantially approach zero voltage level; and subsequently during the data refresh action, charging a new data voltage into the pixel. This feature allows the operation of the dot-matrix display device to have faster speed and low power consumption.

Abstract: A level shifter for a flat panel display device includes: first and second transistors that are different type transistors and serially coupled between first and second power supplies, the second power supply for supplying a lower voltage power than the first power supply; a first capacitor between gate electrodes of the first and second transistors; an input line for a first input signal coupled to the gate electrode of the first or second transistor; a third transistor between a second electrode of the first capacitor and a third power supply, the third transistor having a gate electrode coupled to an input line of a second input signal; and a fourth transistor between the second electrode of the first capacitor and the third transistor, the fourth transistor having first and gate electrodes that are coupled to the second electrode of the first capacitor, such that the fourth transistor is diode-connected.