Patents Examined by Joseph D Manoskey
  • System for sharing processed data between software applications
    Patent number: 10417106
    Abstract: A system includes a first software module, a storage module and a second software module. The first software module receives first data and analyzes the first data to obtain first processed data corresponding to the first data. The storage module stores the first processed data. The second software module receives second data and obtains values in first processed data corresponding to parameters of the second software module, and analyzes the obtained values and the second data to obtain second processed data.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: September 17, 2019
    Assignee: HONGFUJIN PRECISION ELECTRONICS (TIANJIN) CO., LTD.
    Inventor: Shih-Cheng Wang
  • Fault tolerant root cause analysis system
    Patent number: 10417079
    Abstract: Embodiments of the present disclosure relate to a fault tolerant root cause analysis (RCA) system that is able to handle calculation failures during runtime. Calculations (e.g., evaluation of a diagnostic model for a specific component or device) that are performed during the RCA are integrated using different resources of the system under analysis. In order to make a final diagnosis, the resources exchange messages containing calculation inputs and outputs. Calculation problems due to calculation failures in a particular resource can be resolved efficiently which reduces resource utilization and minimizes failure propagation to other parts of the system. Accordingly, the system is able to recover and output a diagnosis even if some of the resources fail or generate problems.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: September 17, 2019
    Assignee: CA, Inc.
    Inventors: Michal Zasadzinski, Marc Sole Simo, Victor Muntes Mulero
  • Memory device with dynamic programming calibration
    Patent number: 10402272
    Abstract: A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine background records associated with a programming step, wherein the background records are for representing previous data operations, calculate a trigger measure based on the background records, wherein the trigger measure is for estimating implementation of an error recovery mechanism, and generate an adjusted step based on the trigger measure.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Larry J. Koudele
  • Method for controlling error rate of device-specific information and program for controlling error rate of device-specific information
    Patent number: 10402248
    Abstract: A method and a program capable of controlling an error rate of device-specific information are provided.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: September 3, 2019
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yohei Hori, Kazukuni Kobara, Toshihiro Katashita, Toshihiro Matsui
  • Preventing data corruption and single point of failure in fault-tolerant memory fabrics
    Patent number: 10402261
    Abstract: An example device in accordance with an aspect of the present disclosure includes a redundancy controller and/or memory module to prevent data corruption and single point of failure in a fault-tolerant memory fabric. Devices include engines to issue and/or respond to primitive requests, identify failures and/or fault conditions, and receive and/or issue containment mode indications.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: September 3, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Derek Alan Sherlock, Harvey Ray
  • Preventing data corruption and single point of failure in a fault-tolerant memory
    Patent number: 10402287
    Abstract: According to an example, data corruption and single point of failure is prevented in a fault-tolerant memory fabric with multiple redundancy controllers by granting, by a parity media controller, a lock of a stripe to a redundancy controller to perform a sequence on the stripe. The lock may be broken in response to determining a failure of the redundancy controller prior to completing the sequence. In response to breaking the lock, the parity cacheline of the stripe may be flagged as invalid. Also, a journal may be updated to document the breaking of the lock.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: September 3, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Derek Alan Sherlock, Harvey Ray, Chris Michael Brueggen
  • IoT device update failure recovery
    Patent number: 10402273
    Abstract: The disclosed technology is generally directed to IoT device update failure recovery. In one example of the technology, after writing an updated release to memory, a determination is made whether the updated release is valid. The updated release includes a plurality of image binaries. If the updated release is determined to be valid, the updated release is made the current release. A determination is made as to whether the current release is stable. Upon determining that the current release is unstable, an auto-rollback is performed. Performing the auto-rollback includes, via at least one processor, automatically: obtaining an uncompressed backup of a previous release; making the uncompressed backup of the previous release the current release; and executing the uncompressed backup.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 3, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Reuben R. Olinsky, Edmund B. Nightingale
  • Ensuring metadata and index consistency using write intents
    Patent number: 10379961
    Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by, receiving a write data object request and writing and committing the data object as a set of encoded data slices into DSN memory. The method continues by writing and committing an index consistency write-intent to DSN memory. The method continues by writing metadata of the data object to DSN memory. The method continues by write and committing an index entry to DSN memory. The method continues, during a finalization of the index consistency write-intent, by executing the index consistency write-intent to ensure consistency between the metadata of the data object and metadata located in the index entry.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel J. Scholl, Jeremy S. Jarczyk, Wesley B. Leggette, Jason K. Resch, Yogesh R. Vedpathak, Manish Motwani, Tyler K. Reid
  • Error recovery in a virtual machine-based development environment
    Patent number: 10379922
    Abstract: The present disclosure relates to error recovery in a virtual machine-based development environment. An example method generally includes monitoring for an error event in a virtual machine managed within a development environment. The development environment attempts to recover the virtual machine from the error event by performing a first error remediation procedure on the virtual machine. Upon determining that the first error remediation procedure failed to recover the virtual machine from the error event, the development environment attempts to recover the virtual machine from the error event by performing a second error remediation procedure on the virtual machine. The second remediation procedure may be a procedure that is more severe than the first error remediation procedure.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: August 13, 2019
    Assignee: INTUIT INC.
    Inventors: Chad Bell, Vinay Kumar, Ryan Lynch, Joseph Elwell
  • Pattern oriented data collection and analysis
    Patent number: 10380001
    Abstract: A process for determining a problematic condition while running software includes: loading a first pattern data set into a volatile memory of a computer, with the first pattern data set being associated with a set of problematic conditions, determining that a runtime symptom code generated while running software on the computer matches a pre-defined symptom code in a set of pre-defined symptom codes, collecting information during runtime according to a set of data collection instructions as a set of collected data, and determining, by applying a set of logic data to the set of collected data, a first problematic condition of the set of problematic conditions triggered the runtime symptom code.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anoop G. M. Ramachandra, Murali K. Surampalli
  • Diagnostic workflow for production debugging
    Patent number: 10380003
    Abstract: A diagnostic workflow file can be used to control the future diagnostic actions taken by a debugger without user interaction with the debugger when it executes. The diagnostic workflow file is used by a debugger during a debug session. The debugger performs the actions directed by the diagnostic workflow file to simulate an interactive live debug session. The diagnostic workflow file can include conditional diagnostic operations whose execution depends on the state of program variables, diagnostic variables and diagnostic primitives in the debug session.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: August 13, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Jackson Davis
  • Distributed system test device
    Patent number: 10372596
    Abstract: Aspects capture test coverage in a distributed system, wherein a processor instigates execution of a unique hypertext transfer request protocol test case within a distributed system of different, networked servers. The header of the unique test case includes a unique name for the unique test case, and the distributed system servers are each configured to, in response to processing a test case, generate a time-stamped log entry that includes header data for the processed test case and a uniform resource locator address of the processing server. The processor thus maps the unique test case to a subset of the distributed system servers as endpoint servers of the unique test case, in response to determining that the uniform resource locator addresses of each of the subset endpoint servers are listed within generated log entries of the endpoint servers in association with the unique test case name.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Adam G. Archer, Herman S. Badwal, Miran Badzak, Robin Y. Bobbitt, Mark T. Duquette, Christopher M. Lee-Shanok, Robert Retchless, Lauren H. Schaefer, Christopher N. Taylor
  • Safe reset techniques for microcontroller systems in safety related applications
    Patent number: 10372545
    Abstract: A microcontroller system includes a processing unit, a first peripheral having a first set of registers, and an assurance module. The first peripheral is configured to receive a first reset signal that resets the first set of registers to a first actual reset value, which is expected to be a first expected value. The assurance module is configured to calculate a first signature value, which is based on the first actual reset value, in response to the first reset signal. The processing unit is configured to perform a first comparison between the calculated first signature value and a pre-determined first signature value to determine whether the microcontroller system is in a trusted safety state. The first comparison is performed in response to the first reset signal, and the pre-determined first signature value is based on the first expected value.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: August 6, 2019
    Assignee: Infineon Technologies AG
    Inventors: Boyko Traykov, Veit Kleeberger, Rafael Zalman
  • Analyzing system for managing information storage table and control method thereof
    Patent number: 10372563
    Abstract: Disclosed are an analyzing system for managing an information storage table and a control method thereof. That is, each of the physical basic regions, which are units of hashing an information storage position, is divided into a plurality of physical sub regions having same size. Then, a combination of virtual basic regions which satisfy a predetermined target value is checked from all configurable combinations and a hash value related with the combination of the virtual basic regions which satisfies the checked target value is stored in a predetermined region of a memory. Therefore, even though an information storage space required for every unit region is overloaded, when there is an extra information storage space in another region, the information storage space having an extra space is used to maximize efficiency of the information storage space.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: August 6, 2019
    Assignee: Korea University Research and Business Foundation
    Inventors: Seon Wook Kim, Ho Kwon Kim, Jae Yung Jun, Young Sun Han
  • Error checking of a multi-threaded computer processor design under test
    Patent number: 10324815
    Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Oz D. Hershkovitz, Gilad Merran, Eyal Naor
  • Service recovery using snapshots and interservice messages
    Patent number: 10318385
    Abstract: An approach is provided in which an information handling system retrieves a snapshot of a first service in response to determining that the first service has failed. The snapshot was captured at a point in time prior to the failure of the first service. The information handling system retrieves a log corresponding to the first service that includes a log entry of a message sent between the first service and a second service that was sent subsequent to the capturing of the snapshot. In turn, the information handling system restores the first service using the snapshot and the message.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jay S. Bryant, James E. Carey, Zachary Hill, Kendall J. Nelson, Lucas A. Palm
  • Hyperconverged infrastructure supporting storage and compute capabilities
    Patent number: 10318393
    Abstract: A hyperconverged data storage system including a storage array. A first node includes hardware and a virtualization layer supporting guest virtual machines running first applications. An active first virtual storage controller executing in the first virtualization layer is configured for handling IOs accessing the storage array. A second node includes hardware and a second virtualization layer supporting guest virtual machines running second applications. A second virtual storage controller executing in the second virtualization layer operates in a standby mode to the first virtual storage controller. An internal communication network facilitates communications between the first node and the second node. The first virtual storage controller when operating in active mode is configured for handling IOs originating from the first applications and the second applications.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 11, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Raja Shekar Chelur Siddalingaiah, Matti Vanninen, Razvan George Costea, Richard Carter, Evan Chiu
  • Systems and methods for eliminating write-hole problems on parity-based storage resources during an unexpected power loss
    Patent number: 10303560
    Abstract: In accordance with embodiments of the present disclosure, a method may include, during a cache flush of data of a cache entry from a non-volatile memory to a storage resource, wherein the non-volatile memory is integral to a persistent write-back cache and storing the data in response to a power event associated with the write-back cache: (a) calculating a calculated parity value by undertaking a read-modify-write operation with respect to the storage resource; and (b) storing the calculated parity value and a target address of the storage resource associated with the calculated parity value in a parity journal.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: May 28, 2019
    Assignee: Dell Products L.P.
    Inventors: Chandrashekar Nelogal, Anand Nunna
  • Storage of mass data for monitoring
    Patent number: 10296435
    Abstract: Disclosed are various embodiments for processing and storing mass data, where the data may include metrics generated based on performance of an event in a monitored system. Metrics describing a state of a monitored system may be received, accessed, and aggregated to generate a data model that describes performance of the monitored system. The metrics utilized in generating the data model may be disregarded after the data model has been generated. An output describing the state of the monitored system may be generated based on the data model, and the output may be communicated over a network, for example, to a requesting service.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 21, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Daniel L. Osiecki, Prashant L. Sarma, Monty Vanderbilt, David R. Azari, Caitlyn R. Schmidt
  • Adjusting trace points based on overhead analysis
    Patent number: 10296436
    Abstract: A computer-implemented method according to one embodiment includes identifying an overhead associated with a tracing of a system, comparing the overhead to a predetermined threshold, and adjusting a number of trace points currently enabled within the system, based on the comparing.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Dean Hildebrand, Vasily Tarasov