Abstract: A priority sorting system for sorting information on a priority basis is disclosed having at least first, second, third and fourth data stores arranged horizontally so that the input of one data store is connected to the output of the preceding data store, and a plurality of comparators, each comparator connected to a pair of data stores with no data store being connected to more than one comparator, said comparators swapping information stored in said data stores on a priority basis.

Abstract: A charge domain parallel processing network. The network includes a floating gate CCD tapped delay line and an array of CCD signal processors each including a charge domain digital-analog multiplier. The delay line holds and shifts analog sampled data in the form of charge packets. At each stage of the delay line a floating gate sensing electrode is coupled to an analog input of an associated one of the CCD signal processors. The sampled data in the respective delay line stages are transferred and subsequently processed in parallel in the processors. Within each processor, the computation functions are performed in the charge domain. In some forms, local charge domain accumulating memories accumulate and store the processed signals, for example, providing a matrix-matrix product network or providing a triple-matrix product network.

Abstract: In a control system for a bidirectional printer capable of printing at different speeds on different lines, stored values representing the ideal velocities during the acceleration and deceleration of the print carriage for each direction and speed are compared with the actual values and any resulting difference is used to move the carriage velocity toward the ideal value.

Abstract: A computer controlled apparatus for grain elevators which includes a computer with keyboard and display and suitable output devices such as a printer and which receives inputs from sensing devices such as scales and moisture analyzers and sensors and which records and retains grain transactions as the grain is weighed and unloaded and in which samples of the grain are selected and analyzed in a moisture meter. The elevator operator inputs with the keyboard particular customer numbers and other desired information and the apparatus eliminates weigh ticket writing and prints over the scale transactions automatically and provides instant decision data such as marketing data so that the accounting functions can be automatically selected.

Abstract: A programmable automatic controller for operating a section of a glassware forming machine having a plurality of components which operate in a timed or sequential relationship with one another. The controller includes a timing means for generating cycle clock pulses in synchronism with the operation of the machine, wherein the cycle clock pulses provide an instantaneous indication of the time elapsed in each cycle of operation of the machine. A random access memory (RAM) stores the relative times during each cycle of machine operation when each of the plurality of machine components are to be enabled and/or inhibited. When the time elapsed in a cycle corresponds to a component actuating time stored in the running storage, an actuating signal is generated by a comparator. This signal is coupled to a machine component addressing arrangement which provides a component enable or inhibit command signal to the addressed component whose actuating time compared to the cycle time elapsed.

Abstract: A data transmission system comprising a plurality of terminal units each having at least one input and at least one output connected such that each connected input of a terminal unit is connected to a connected output of another terminal unit. Each terminal unit with at least two input connections comprises a changeover switch to provide for incoming signal induced connecting of one of the inputs to a receiver circuit for recognizing and receiving certain signals. A test circuit is connected to the receiver circuit for determining if the test signals received are free from errors. An error sum counter is connected to the test circuit and to the changeover switch. At least one of the terminal units comprises an emitting provision for test signals, which is connected to the outputs of the terminal unit to provide for checking of the functioning of the transmission system. For each missing or defective test signal train received an error message is fed to the error sum counter for increasing the count value.

Abstract: The storage locations of a memory system map a field of sample points. Apparatus affording parallel access to a plurality of storage locations describing an array of the sample points in an access window, which window can be shifted to any selected region of field of sample points responsive to orthogonal address coordinates of one of the sample points in the array, is described.

Abstract: A control system for a bidirectional printer having a print head carriage movable at different speeds on different printing lines provides for equal stopping distance in the margin at both high and low speed operation. This is accomplished by delaying the initiation of stopping carriage motion when printing at low speed so that the carriage travels farther into the margin and this distance is controlled so as to be equal to the travel distance at the end of a line printed at high speed.

Abstract: An information processing system is disclosed which includes a display, a memory, a keyboard and a control unit. The system may store and display data in a table format by record and field. The system may be employed in an entry edit mode whereby data is entered or edited by an operator through the keyboard into the system. The system may also operate in a record selection mode whereby data in a field having a predetermined relation to a field value may be selected by the system. The system permits the entry of comparison operators and field values below the field heading in the display for the field to be searched. The keys representing the comparison operators and the keys representing data are at separate locations on the keyboard to prevent operator error in input. This feature is particularly advantageous when one symbol may be employed both as a comparison operator and data. Such a symbol would then be represented by two keys on the keyboard.

Abstract: A control system comprises several slave modules each operative to control a specific function and a master module operative to control all the slave modules. Each slave module comprises a processing circuit cooperating with an input/output interface permitting conversation with the operator and a memory circuit intended to specify the function which must be controlled by the slave module. The master module comprises a processing circuit cooperating with a memory for the conversation software and for processing the information received by the slave modules, and with an input/output interface permitting conversation with the operator. All the modules are interconnected on the one hand by a conversation bus between the modules and, on the other hand, by a master bus which enables the master module to read directly into a memory of each slave module the additional software necessary for conversation with the slave module.

Abstract: In a control system for a bidirectional printer capable of printing at different speeds on different lines and in which the actual velocity of the print carriage is compared with a desired velocity profile to generate an error count, the error count is measured and averaged out for each direction and speed of carriage movement to compensate for the effect of changes in the printer system dynamics such as aging, wear, debris buildup, etc.

Abstract: A synthesizer comprises a basic synthesizer (1) generating a frequency Fo+.xi., wherein .xi. can be varied by small incremental steps, and a phase-locking loop (including a divider 2, a comparator 3, a filter 6, a mixer 4) setting the frequency of an intermediate oscillator (5) to a value Fi=(Fo+.xi.)/(NR+M), wherein NR+M is the division rate of divider 2. A fractional multiplier including an output oscillator 8, a mixer 9, harmonic generators 7 to 12, a divider 13 and a phase comparator 11 multiplies intermediate oscillator frequency Fi by N+(M/R), wherein R preferably is 5. The synthesizer can be used to synthesize frequencies up to several gigahertz.

Abstract: A charge domain digital-analog multiplier device. The device has one analog input, M-parallel digital inputs, and one analog output. An M-bit digital word signal is applied to the digital inputs and an analog signal is applied to the analog input. The output is a charge packet which is proportional to the product of the analog input signal and the digital word.

Abstract: A data byte element E located at position d in entry i of memory section M.sub.a having reference entry TR is addressed. Memory section M.sub.a is one section of a table in a data processory memory, such that each of the entries in section M.sub.a has a predetermined number (t) of elements E. Signals having values related to the values of i, t and TR of several memory sections are stored in a storage device and read out when the storage device is addressed. A signal related to the value of d is also derived as a result of read-out from the storage device. The signals having values related to the values of i, t, TR and d are combined to derive an addressing signal for element E in memory section M.sub.a of the table of the data processing memory. An address circuit for the data processing memory responds to the addressing signal to addressing element E in memory section M.sub.a.

Abstract: A numerical machine tool control has several processors. A monitoring circuit is associated with each processor which, upon the appearance of a predetermined address, interrupts the address stepping action in all processors by an interrupt command with highest priority and switches to the servicing mode. The stored data assigned to the respective addresses and the states of the overall system can be interrogated successively from the operating panel and changed, if necessary.

Abstract: In a system which performs tracer control by calculating the direction and velocity of tracing using signals from a tracer head tracing the model surface, there are provided an input unit for entering data defining the tracing operation, a memory for storing the data and a processor for reading out the data from the memory to control respective parts of a control device. Of the data defining the tracing operation, stored in the memory, data concerning the reference displacement of the tracer head is read out by the processor to change the reference displacement for each profile modeling operation, thereby automatically performing repetitive tracing.

Abstract: A method and apparatus for determining the time remaining for maximum control action to be taken in order to achieve a desired objective (i.e., the chronodrasic interval) is disclosed. The method and apparatus continuously determines the amount of a parameter (e.g., runway distance) required to achieve a desired objective (e.g., stopping an aircraft before reaching the end of a runway on landing or accelerating an aircraft so that it reaches rotation speed before reaching the end of a runway on takeoff) if maximum control action is applied. The method and apparatus also continuously determines the total amount of the parameter remaining. The chronodrasic interval is then determined by deducting the amount of the parameter required to achieve the desired objective if maximum control action is taken from the total amount of the parameter remaining; and, dividing the result by a preselected (e.g., present or maximum) rate of change of the parameter.

Abstract: In order to keep the number of data transfers small in storing bit pattern fields in an external memory, only the first line and the changed data of the bit pattern field are transmitted and the field is reconstructed line by line by means of an interim register and then stored. For this purpose the interim register has, besides a data input connected with the bit pattern field and an input for a STROBE signal, an input for addressing register locations corresponding to those memory building blocks, the data of which has changed from line to line. Advantageously, groups of eight memory building blocks, to which an interim register in the form of an 8-bit decoder register is assigned, are used.

Abstract: A manipulator and control are provided for moving a function element carried by the manipulator in accordance with programmed input signals defining positions and path velocities therebetween of a tool centerpoint associated with the function element. The path velocity is made susceptible of variation in accordance with unprogrammed variations of a parameter manually or automatically produced. Motion of the tool centerpoint is effected by interpolation of intermediate point along a predetermined path between any two preprogrammed positions. Each intermediate point is displaced from its predecessor by an increment computed in accordance with a fixed increment interval period and an instantaneously variable increment velocity. Incremental velocity values are computed selectively in accordance with a simple function relating the variable parameter and velocity and in accordance with the preprogrammed definition of motion.

Abstract: A digital timing system for sports competitions in which a large number of participants progress independently and simultaneously on the same track between a starting line and a finish line. This system comprises a starting time memory, a finish time memory, and a register which permits the temporary storing of the times of a predetermined number of events happening nearly simultaneously. The time is furnished by means of an oscillator and decade counters of which the multiplexed output is applied to the register where the information is entered. This information is shortly thereafter transferred to the starting time memory or to the finish time memory, as the case may be. A subtractor unit subtracts the recorded starting time of a selected participant from the real time when it is desired to display the lapsing time of the participant. At the final, the final track time is displayed.