Patents Examined by Joseph O Schell
  • Patent number: 12650910
    Abstract: The present invention relates to a method and an apparatus for detecting anomalies in an operation behavior of a device under test (DUT), in particular during electromagnetic susceptibility (EMS) measurements. The apparatus comprises a monitoring unit adapted to generate a first set of observation data of the operation behavior of a DUT while the DUT is not subjected to disturbances and adapted to generate a second set of observation data of the operation behavior of a DUT while the DUT is subjected to disturbances and comprising an AI module trained with the first set of observation data generated by the monitoring unit and adapted to process the second set of observation data to detect anomalies in the operation behavior of the DUT while being subjected to the disturbances and comprising a reporting unit adapted to reporting anomalies in the operation behavior of the DUT detected by the trained AI module.
    Type: Grant
    Filed: February 6, 2024
    Date of Patent: June 9, 2026
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Hendrik Bartko, Rafid Ahmed, Reiner Goetz, Georg Schwarz
  • Patent number: 12645481
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for state convergence associated with high availability application migration in a virtualized environment. An example apparatus includes at least one memory, machine readable instructions, and processor circuitry to at least one of execute or instantiate the machine readable instructions to identify a high availability slot in a virtual server rack including a first virtual machine (VM) associated with first configuration data that identifies the first VM as a protected VM, transmit second configuration data to a second VM that identifies the first VM as a nonprotected VM and the second VM as the protected VM, after a determination that a network partition is identified based on a failure of a request to retrieve the second configuration data from the second VM, and transfer data from the first VM to the second VM after causing the removal of the network partition.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: June 2, 2026
    Assignee: VMware LLC
    Inventors: Deepak Babarjung, Brian Masao Oki, Maarten Wiggers, Ivaylo Radoslavov Radev, Sandeep Sinha
  • Patent number: 12645520
    Abstract: Memory with fail indicators, and associated systems, devices, and methods are disclosed herein. In one embodiment, a system includes a plurality of memory systems and a host device. At least one of the memory systems includes a fail indicator connected to the host device via a side channel of the system. The host device is configured to detect an occurrence of a failure on the at least one memory system and to initiate activation of the fail indicator. The side channel can be an I2C or I3C® side channel. The fail indicator, when activated, can provide a visual indication of the failure. For example, the fail indicator can include an LED that can be activated to emit light and provide an indication of the failure. A color of the light can correspond to a type, occurrence, or location of the failure on the at least one memory system.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: June 2, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Aaron Jannusch, Mow Yiak Goh, Robin K. Mitra
  • Patent number: 12632353
    Abstract: A Data Storage Device (DSD) is represented by an embedding for virtual testing. A plurality of metrics is obtained for components of the DSD and is encoded into the embedding using a first Artificial Intelligence (AI) model. The embedding is provided as an input to a second AI model configured for virtual testing based on one or more simulated DSD workloads. In one aspect, virtual testing is performed for at least one DSD component by obtaining at least one metric for the at least one component for encoding into an embedding representing a virtual DSD including the at least one component. In another aspect, the embedding is provided to a DSD operator for virtual testing. In yet another aspect, the second AI model simulates at least one workload of the DSD operator or for one or more quality assurance tests of a DSD manufacturer.
    Type: Grant
    Filed: June 21, 2024
    Date of Patent: May 19, 2026
    Assignee: Western Digital Technologies, Inc.
    Inventors: Donald Penza, Natasa Letourneaut, Vish Vuggumudi
  • Patent number: 12619493
    Abstract: Described apparatuses and methods provide configurable error correction code (ECC) circuitry and schemes that can utilize a shared ECC engine between multiple memory banks of a memory, including a low-power double data rate (LPDDR) memory. A memory device may include one or more dies with multiple memory banks. The configurable ECC circuitry can use an ECC engine that services a memory bank by producing ECC values based on data stored in the memory bank when data-masking functionality is enabled. When data-masking functionality is disabled, the configurable ECC circuitry can use the shared ECC engine that services at least two memory banks by producing ECC values with a larger quantity of bits based on respective data stored in the at least two memory banks. By using the shared ECC engine responsive to the data-masking functionality being disabled, the ECC functionality can provide higher data reliability with lower die area utilization.
    Type: Grant
    Filed: September 10, 2024
    Date of Patent: May 5, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Keun Soo Song, Kang-Yong Kim, Hyun Yoo Lee
  • Patent number: 12602301
    Abstract: A test control process initiates processing of a test case to be used in system level testing of a system unit under test. A query is sent, by the test control process, to a central test manager to determine a history of the test case. The history of the test case is obtained by the test control process based on the query. Processing of the test case continues, based on the history.
    Type: Grant
    Filed: November 10, 2023
    Date of Patent: April 14, 2026
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edward C. McCain, Rajani Guduru, Ali Y. Duale, Zahed Hossain
  • Patent number: 12596599
    Abstract: Techniques for providing a centralized framework for forecasting IT component failures. The techniques include collecting raw telemetry data specific to different IT component domains, and transforming the telemetry data into structured telemetry data. The techniques include performing feature engineering on the structured telemetry data to obtain features relevant to IT component failures in each IT component domain, and, for each IT component domain, using the features to generate a customized ML model. The techniques include accessing features relevant to IT component failures in each IT component domain, accessing a customized ML model for forecasting IT component failures in the IT component domain, and forecasting IT component failures in the IT component domain using the customized ML model.
    Type: Grant
    Filed: August 5, 2024
    Date of Patent: April 7, 2026
    Assignee: Dell Products L.P.
    Inventors: Arun Rameshbabu, Shaul Dar, David Sydow, Shreyans Jasoriya, Keith Drummond, Nicolas Leazard
  • Patent number: 12591495
    Abstract: The present invention provides a multimedia product burn-in apparatus configured to test several multimedia products, including: a controller, configured to issue a running command; and a network server, connected to the controller and the several multimedia products respectively, the network server storing a test file, and the test file being generated by matching a signature and a log of the multimedia product, where the network server receives the running command to generate a control command, sends the test file to the several multimedia products according to the control command, and performs batch testing on the several multimedia products. The multimedia product burn-in apparatus saves a tester from repeatedly making individual changes to each multimedia product, achieves automated testing, and solves the problem of high manpower, material, and time costs caused by batch bum-in of the multimedia products in research and development and design stages.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: March 31, 2026
    Assignee: AMLOGIC (SHANGHAI) CO., LTD
    Inventors: Yuan Luo, Fengping Xiong, Kang Jiang
  • Patent number: 12578384
    Abstract: Technologies for a unified debug and test architecture in chiplets is disclosed. In an illustrative embodiment, several chiplets are integrated on an integrated circuit package. The chiplets are connected by a package interconnect, such as a universal chiplet interconnect express (UCIe) interconnect. Each chiplet includes several debug nodes, which are connected by an on-chiplet network. One of the chiplets, referred to as a package debug endpoint, acts as a link endpoint for an off-package link, such as a peripheral component interconnect express (PCIe) link. In use, debug messages can be sent to the package debug endpoint over a PCIe link. The debug messages can be routed within the chiplets and between chiplets, allowing for the debug functionality at each debug node to be probed using a common protocol. In this manner, chiplets from different vendors can be integrated into the same package and tested using common software.
    Type: Grant
    Filed: December 12, 2023
    Date of Patent: March 17, 2026
    Assignee: Intel Corporation
    Inventors: Sridhar Muthrasanallur, Debendra Das Sharma, Swadesh Choudhary, Gerald Pasdast, Peter Onufryk
  • Patent number: 12579027
    Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including storing a set of user data and multiple portions of error correction data. The operations can also include, responsive to an expiration of a first threshold amount of time after storing the set of user data, performing, using the third portion of the error correction data, a first error correction operation, on each of the set of user data, the first portion, and the second portion, and rewriting, on the memory device, the set of user data, the first portion, and the second portion. The operations can further include deleting the third portion.
    Type: Grant
    Filed: June 18, 2024
    Date of Patent: March 17, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Dung Viet Nguyen, James Fitzpatrick, Huai-Yuan Tseng
  • Patent number: 12579033
    Abstract: Disclosed in the embodiments of the present application are a data storage method and apparatus, a device, and a non-transitory readable storage medium. According to the embodiments of the present application, F parity blocks occupying blank storage areas are added to a RAID system, which not only increases error tolerance but also eliminates the need for additional parity disks. During data storage, corresponding original check codes are solved according to an original encoding method, and additional check codes located on the parity blocks are solved simultaneously. Thus, it is possible to recover more erroneous data based on the original check codes and the additional check codes. When an error occurs in a disk in which any block in a stripe is located and data loss occurs in other blocks of the same stripe, the corresponding data can still be recovered.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: March 17, 2026
    Assignee: SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Ruizhen Wu, Yongxing Zhang, Jingjing Chen, Xu Zhang, Lin Wang, Tong Liu
  • Patent number: 12572414
    Abstract: A multimode solid-state drive (SSD) and associated method. An SSD includes: a plurality of flash memory chips addressable via a physical block address (PBA); and a controller chip configured to map logical block addresses (LBAs) from a host to PBAs, wherein the controller chip is further configured to handle different LBA block sizes according to a process that includes: partitioning a base partition to store one a long code word of size Clong having a single base data block protected with error correction coding (ECC); and partitioning a set of non-base partitions, each partitioned for a plurality of shortened code words, wherein each shortened code word is configured to store a shortened data block protected with ECC, and wherein the plurality of shortened code words are configured to be protected with ECC as a combined long codeword of size Clong.
    Type: Grant
    Filed: February 20, 2024
    Date of Patent: March 10, 2026
    Assignee: SCALEFLUX, INC.
    Inventors: Tong Zhang, Mark Vernon, Ganesh Venkatakrishnan, Yang Liu, Fei Sun
  • Patent number: 12572420
    Abstract: A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that can correct residual bit errors. The bit errors correctable by the ECC schemes not only include those errors that have been existing in input data used for the RAID process, but also those bit errors may have been propagated due to the existing errors.
    Type: Grant
    Filed: February 16, 2024
    Date of Patent: March 10, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. McCrate, Marco Sforzin, Paolo Amato, Brian M. Twait
  • Patent number: 12561192
    Abstract: Examples of the present disclosure describe systems and methods determining a root cause of an outage of a dependent service. A method includes detecting an outage of a dependent service, determining a first service dependency of the dependent service, and identifying one or more instances of the first service dependency by accessing a service provider of the first service dependency. The method also includes collecting one or more service level indicators (SLIs) for one or more instances of the first service dependency and determining a health status of the instances of the first service dependency using the SLIs. The method further includes determining a root cause for the outage of the dependent service based on the health status of the instances of the first service dependency.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: February 24, 2026
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sarit Pinahs, Izhak Mashiah, Offek Anker, Liron Mid, Yosef Asaf Levi, Tamar Agmon, Muhamed awad Mhameed, Idan Agam
  • Patent number: 12561190
    Abstract: A system and method for discovering fault conditions such as conflicts between applications and an operating system, driver, hardware, or a combination thereof, installed in mobile computing devices uses a mobile device running a diagnostic application. A list of applications that were launched or installed during a time period prior to an operational disruption is retrieved. A data table of combinations of incompatible programs and drivers is used to analyze the list of the applications that were launched or installed to create a list of potential fault-causing interactions due to software incompatibilities of software installed in the mobile computing device. A knowledge database is updated with data identifying at least one of the potential fault-causing interactions.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: February 24, 2026
    Assignee: Future Dial, Inc.
    Inventor: George Huang
  • Patent number: 12554587
    Abstract: High availability and disaster recovery for replicated object stores is disclosed. An embodiment includes receiving, by a first storage system of a plurality of storage systems symmetrically replicating objects of a bucket, a request to establish immutable content for the bucket; indicating, by the first storage system to a second storage system of the plurality of storage systems, the request to establish immutable content, wherein the second storage system establishes an ordering for conflicting requests of different storage systems to establish immutable content for the bucket; and processing, by the first storage system, the request based on ordering information received from the second storage system.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: February 17, 2026
    Assignee: PURE STORAGE, INC.
    Inventor: Ronald Karr
  • Patent number: 12554605
    Abstract: A hardware accelerator includes a plurality of functional circuits, a stream switch, a plurality of direct memory access (DMA) channels coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, and a debug and trace unit coupled to the stream switch, wherein in operation, the debug and trace unit monitors a set of data signals to and from the stream switch via wired probes and implements one or more event counters, one or more triggers, and one or more tracers using components internal to the hardware accelerator including one or more registers of the hardware accelerator, and wherein the one or more tracers output trace data packets via the stream switch.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: February 17, 2026
    Assignee: STMicroelectronics International N.V.
    Inventors: Antonio De Vita, David Siorpaes, Thomas Boesch, Giuseppe Desoli
  • Patent number: 12530269
    Abstract: A method for monitoring a clock generator module of an electronic circuit which is configured to generate a plurality of clock signals for the electronic circuit. A monitoring module external to the circuit alternately causes the selection of one of the clock signals in the circuit as a selection signal; wherein based on the selection signal a PWM signal, whose period duration and holding time are predetermined, is generated and output; wherein the PWM signal is received from the electronic circuit by the monitoring module and measured using a monitoring clock signal to determine at least one measurement result, the at least one measurement result is compared with at least one comparison result or comparison result range, and a malfunction of the clock generator module is determined if the at least one measurement result does not match the at least one comparison result or comparison result range.
    Type: Grant
    Filed: January 10, 2024
    Date of Patent: January 20, 2026
    Assignee: Robert Bosch GmbH
    Inventors: Carsten Mitter, Sai Gautam Janaki Premkumar
  • Patent number: 12517797
    Abstract: A data storage system and method comprising: at least two servers that comprise a RAID 1 storage volume and configured to run an operating system designated to host data accessible and exposable over a data plane (DP) network, wherein the servers are located remotely from each other, and wherein the RAID 1 is configured to be utilized for a remote replication procedure while connecting the two volumes of the at least two servers.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: January 6, 2026
    Assignee: VOLUMEZ TECHNOLOGIES, LTD.
    Inventor: Jonathan Amit
  • Patent number: 12517765
    Abstract: A framework that may be implemented by a workload orchestration platform for scheduling accelerator-enabled workloads on the accelerators in a cluster is provided. In one set of embodiments, the framework enables the platform to schedule accelerator-enabled workloads based on a multitude of user-provided, fine-grained accelerator requirements. In another set of embodiments, the framework enables the platform to automatically recommend an initial set of accelerator resource requirements for an accelerator-enabled workload and automatically right-size such requirements based on telemetry data collected during the workload's runtime.
    Type: Grant
    Filed: August 14, 2023
    Date of Patent: January 6, 2026
    Assignee: VMware LLC
    Inventors: Nilanjan Daw, Hari Sivaraman, Uday Pundalik Kurkure, Sairam Veeraswamy, Lan Vu