Abstract: A superscalar microprocessor is provided that includes a predecode unit configured to predecode variable byte-length instructions prior to their storage within an instruction cache. The predecode unit is configured to generate a plurality of predecode bits for each instruction byte. The plurality of predecode bits, called a predecode tag, associated with each instruction byte include a number of bits that indicates a number of byte positions to shift each instruction byte in order to align the instruction byte with a decode unit. Each decode unit includes a fixed number of instruction byte positions for storing bytes of instructions. A start byte of an instruction is conveyed to a first instruction byte position. The predecode tags are used by a multiplex and shift unit of an instruction alignment unit to shift the instruction bytes such that the start byte of an instruction is stored in a first instruction byte position of a decode unit.

Abstract: A method for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.