Patents Examined by Joseph R Kudirka
  • Patent number: 10838803
    Abstract: Embodiments for preemptive deep diagnostics of resources in a disaggregated computing environment. A set of new resources of a first type is provided to an available resource pool within the disaggregated computing environment. An estimate for an expected time to failure (ETTF) for each one of the set of new resources is computed, and respective ones of the new resources from the available resource pool are provisioned to respective workloads based on the ETTF.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruchi Mahindru, John A. Bivens, Min Li, Valentina Salapura, Eugen Schenfeld
  • Patent number: 10831628
    Abstract: A method to check for redundancy in two or more data lines comprises receiving data on a first data line, computing a first cyclic redundancy check (CRC) value on the data of the first data line, performing an exclusive OR (XOR) function on the first CRC value with a stored memory value, and updating the stored memory value with a result of the XOR function, and repeating on additional data lines until a last line is processed such that an error is indicated if a final stored memory value is not zero. An apparatus to check that two cores are operating in lockstep comprises a first core comprising a first data checker, a second core comprising a second data checker, and a lockstep checker to compare an output of the first data checker with an output of the second data checker.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Umberto Santoni, Rahul Pal, Philip Abraham, Mahesh Mamidipaka, C Santhosh
  • Patent number: 10831617
    Abstract: An information processing system, computer readable storage medium, and method for supporting resilient execution of computer programs. A method provides a resilient store wherein information in the resilient store can be accessed in the event of a failure. The method periodically checkpoints application state in the resilient store. A resilient executor comprises software which executes applications by catching failures. The method uses the resilient executor to execute at least one application. In response to the resilient executor detecting a failure, restoring application state information to the at least one application from a checkpoint stored in the resilient store, the resilient executor resuming execution of the at least one application with the restored application state information.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Arun Iyengar, Joshua J. Milthorpe
  • Patent number: 10831616
    Abstract: An information processing system, computer readable storage medium, and method for supporting resilient execution of computer programs. A method provides a resilient store wherein information in the resilient store can be accessed in the event of a failure. The method periodically checkpoints application state in the resilient store. A resilient executor comprises software which executes applications by catching failures. The method uses the resilient executor to execute at least one application. In response to the resilient executor detecting a failure, restoring application state information to the at least one application from a checkpoint stored in the resilient store, the resilient executor resuming execution of the at least one application with the restored application state information.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Arun Iyengar, Joshua J. Milthorpe
  • Patent number: 10824525
    Abstract: Method and apparatus for a system to detect, address, and resolve defects, disfunctions, and inefficiencies in a distributed data environment. One or more diagnostics monitor specific operating parameters of specific services operating within the distributed data environment. When the diagnostic detects a service operating outside of a pre-determined threshold, an alert message is issued. Appropriate responses to the alert message assures that the system will maintain high availability protocol and will operate efficiently.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: November 3, 2020
    Assignee: Bank of America Corporation
    Inventors: Todd Lowney, Velmurugan Vinayakam, Frederick L. Anderson
  • Patent number: 10824499
    Abstract: An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chaohong Hu, Hongzhong Zheng, Uksong Kang, Zhan Ping
  • Patent number: 10824530
    Abstract: In one embodiment, an apparatus includes a controller to couple between a system on chip (SoC) and an external connector of a platform. The controller may include: a digitizer to digitize platform telemetry information of the platform; and a control circuit to receive a command from a debug test system and direct the platform telemetry information to a destination in response to the command. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Rolf H. Kuehnis, Sankaran M. Menon, Rob W. Sims
  • Patent number: 10819762
    Abstract: A system for delivering content over a network includes a server. The server is configured to divide the content into multiple segments, to create multiple data streams using the segments of the content, and to transmit each of the data streams via a respective multicast session, wherein a copy of each of the multiple segments is transmitted during a single time slot of the multicast session.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 27, 2020
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Douglas M. Nortz, Mark W. Altom, Robert J. Sayko
  • Patent number: 10819334
    Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 27, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Chunhua Hu, Venkateswar Reddy Kowkutla, Charles Fuoco
  • Patent number: 10813202
    Abstract: A lighting fault diagnosis method includes determining a fault item among a plurality of fault items based on fault symptom data of a test for each fault item, and recommending a repair method suitable for the determined fault item.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: October 20, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyunseok Kim, Tae-Gyu Kang, Dae Ho Kim, You Jin Kim, Ji Hun Jeon
  • Patent number: 10809779
    Abstract: An apparatus and method thermally manage a high performance computing system having a plurality of nodes with microprocessors. To that end, the apparatus and method monitor the temperature of at least one of a) the environment of the high performance computing system and b) at least a portion of the high performance computing system. In response, the apparatus and method control the processing speed of at least one of the microprocessors on at least one the plurality of nodes as a function or at least one of the monitored temperatures.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: October 20, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Eng Lim Goh, Patrick Donlin, Andrew Warner
  • Patent number: 10795774
    Abstract: Methods and systems for efficiently downloading archived snapshot data from the cloud or from an archival data store are described. In a disaster recovery scenario in which an entire storage appliance for backing up different point in time versions of a virtual machine has failed (e.g., due to a fire), archived snapshot data for the different point in time versions may be acquired by a second storage appliance from an archival data store (e.g., cloud-based data storage) using one or more snapshot mapping files. A snapshot mapping file may include pointers to a plurality of data blocks within the archival data store for generating a full image snapshot associated with a particular point in time version of the virtual machine. The plurality of data blocks may comprise the minimum number of data blocks necessary to construct the particular point in time version of the virtual machine.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 6, 2020
    Assignee: Rubrik, Inc.
    Inventors: Prateek Pandey, Arpit Agarwal
  • Patent number: 10789265
    Abstract: A system for migrating data from a legacy system to a target system includes an input/output (IO) processor configured to receive legacy data from a plurality of different types of legacy systems and to communicate target data to a plurality of different types of target systems; a staging area database configured to store legacy data according to a common database schema; a localized database configured to store target data according to a target schema that is associated with a target system type; a processor in communication with the interface, the staging area database, and the localized database; and non-transitory computer readable media in communication with the processor that stores instruction code.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 29, 2020
    Assignee: Accenture Global Solutions Limited
    Inventors: Sanjay Tiwari, Devendra Gautam, Nithyanandan Periasamy Dhanapal, Surya Kumar Venkata Gangadhara Idumudi, Nikhil Varshney, Ranjana B Narawane
  • Patent number: 10789157
    Abstract: According to at least one aspect, a system is provided. The system comprises at least one hardware processor; and at least one non-transitory computer-readable storage medium storing processor executable instructions that, when executed by the at least one hardware processor, cause the at least one hardware processor to perform: monitoring execution of a first computer program configured to control a second computer program to perform a task at least in part by controlling the second computer program, through a graphical user interface (GUI) and/or an application programming interface (API) for the second computer program, to perform at least one action in furtherance of the task; detecting at least one anomaly in the execution of the first computer program; and outputting the detected at least one anomaly in the execution of the first computer program.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: September 29, 2020
    Assignee: Soroco Private Limited
    Inventors: Nishant Kumar Jain, Rohan Narayan Murty, George Peter Nychis, Harsh Gupta, Yoongu Kim
  • Patent number: 10783049
    Abstract: In one embodiment, virtual storage drives are allocated to RAID arrays so that no two virtual storage drives of a RAID array are mapped to the same physical storage drive. In another aspect, error handling routines are limited to virtual storage drives impacted by an error in a physical storage drive so that virtual storage drives of the physical storage drive not impacted by the error are bypassed. In yet another aspect, cache operations to a target virtual storage drive may be throttled as a function of both a limit imposed on cache operations directed to the RAID array to which the virtual storage drive is allocated, and a separate limit on cache operations directed to a group of virtual storage drives which are mapped to the same physical storage drive as the target virtual storage drive. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Kevin J. Ash, Karl A. Nielsen
  • Patent number: 10769056
    Abstract: A system for autonomously testing a computing system is disclosed. The system parses data obtained from a variety of sources, and extracts source concepts from the parsed data to generate models for inclusion in a set of agglomerated models. The system interacts with and explores features of a software application being tested by the system. Outputs and information obtained from the interaction are utilized by the system to update the models or generate new models for the set of agglomerated models. The agglomerated models are utilized by the system to execute tests on the application to detect potential defects and conflicts. Detected defects and conflicts may be included in a report for review. Feedback on the defects and conflicts may be utilized to further update the agglomerated models. The agglomerated models are updated recursively as additional data is obtained, further interactions are performed, and further outputs are generated over time.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 8, 2020
    Assignee: The Ultimate Software Group, Inc.
    Inventors: John A. Maliani, Robert L. Vanderwall, Michael L. Mattera, Dionny Santiago, Brian R. Muras, Keith A. Briggs, David Adamo, Tariq King
  • Patent number: 10761916
    Abstract: A method for executing programs (P) in an electronic system for applications with functional safety that comprises a single-processor or multiprocessor processing system (10) and a further independent control module (15), including: carrying out a decomposition of a program (P) that includes a safety function (SF) to be executed via said system (10) into a plurality of parallel subprograms (P1, . . . , Pn); assigning execution of each parallel subprogram (P1, . . . , Pn) to a respective processing module (11) of the system, in particular a processor (C1, . . . , Cm) of said multiprocessor architecture (10) or a virtual machine (V1, . . . , Vn) associated to one of said processors (C1, . . . , Cm); carrying out in the system (10), periodically according to a cycle frequency (fcyc) of the program (P) during normal operation of said system (10), in the context of said safety function (SF), self-test operations (Astl, Asys, Achk) associated to each of said subprograms (P1, . . .
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventor: Riccardo Mariani
  • Patent number: 10755193
    Abstract: One or more time correlations of noise within a quantum computing circuit of a quantum processor are determined. The quantum computing circuit includes one or more qubits. A coherence time for each qubit is determined, and one or more stretch factors are determined based upon the time correlations of the noise and the coherence times. A first loop is initialized that performs for each of the stretch factors: initializing the qubits to a ground state, executing the quantum computing circuit with a the stretch factor, performing one or more single-qubit post-rotations associated with one or more expectation values, measuring a state of each qubit to determine the one or more expectation values of interest, and resetting each qubit to the ground state. A mitigated estimate is determined for the expectation values based upon an extrapolation of the expectation values determined for each stretch factor.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abhinav Kandala, Paul Kristan Temme, Jay M. Gambetta
  • Patent number: 10754760
    Abstract: Disclosed approaches involve at least one processor executing a program and a debug interface circuit coupled to the processor. The debug interface circuit is configured to transmit first trace data from the first processor. A debug access port is coupled to the debug interface circuit. A fault detection circuit is coupled to the debug access port and is configured to receive the first trace data via the debug access port and compare the first trace data to second data. The fault detection circuit generates an error signal to the first processor in response to a discrepancy between the first trace data and the second data.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 25, 2020
    Assignee: Xilinx, Inc.
    Inventors: Paul S. Levy, Giulio Corradi
  • Patent number: 10747439
    Abstract: Power-fail safe compression and dynamic capacity for a storage device in a computer system is provided. Metadata stored with each logical block in non-volatile memory in the storage device ensures that the mapping table may be recovered and stored in volatile memory for use by the computer system after power is restored to the computer system. In addition, the metadata ensures that a list of free logical block addresses written to the storage device prior to shutting down the computer system to provide access to the additional capacity that is available in the storage device by storing compressed data in the storage device may also be recovered.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Rowel S. Garcia, Sanjeev N. Trika, Jawad B. Khan