Abstract: An apparatus for serial data communication between a plurality of IC chips with a reduced number of inter-chip signal lines. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to it. In response to conditions internal to the master chip or in response to a request from at least one of the slave chips, the master chip generates a transfer control signal and a synchronization clock signal. The transfer control signal defines a transfer phase during which data transfer among the chips can take place. The chips take turns sending and receiving data in a multiplexed fashion, with sending and receiving parties designated by a count of synchronization clock signal cycles. The synchronization clock signal is generated at a high frequency, to allow fast data transfer.

Abstract: A memory efficient time de-interleave, de-puncture and viterbi decoder circuit is provided for decoding frames of digital data that is time interleaved over a plurality of data frames, wherein the time interleaved digital data includes convolutionally encoded data. The circuit includes a time de-interleave block having an input receiving a stream of the digital data and an output connected to an input of a de-puncture block, which has an output connected to an input of a viterbi decoder block. The time de-interleave block is adapted for communication with an external memory wherein the time de-interleave block establishes a plurality of address pointers thereto corresponding to the plurality of time interleaved data frames. In accordance with the address pointers, the time de-interleave circuit stores the viterbi metric data for a number of data frames within the external memory in a storage efficient manner.

Abstract: A cordless telephone system connectable to the public switched telephone network having a base station and one or more handsets communicating with the base station by an RF link using a time division duplex direct sequence spread spectrum quadrature modulation technique, having a gain imbalance compensation system for balancing the gain between the I and Q channels. Gain imbalance estimation is performed as part of a calibration cycle when the handset is in the cradle of the base station. The controller of the unit causes another unit to send a data signal with a frequency error. The baseband receiver performs the operation .vertline.I.vertline.-.vertline.Q.vertline., which is an indication of gain error. The results are stored in an accumulator over a set period of time. The controller reads the accumulator and uses an iterative process, increasing or decreasing the gain link compensation until no gain imbalance error is obtained.

Abstract: For use in a direct sequence spread spectrum ("DSSS") receiver adapted to receive a differential phase shift keyed ("DPSK") packet on a channel, the DPSK packet having a training preamble and a data portion, a system to improve detection of the packet under degraded channel conditions, comprising: (1) a detection circuit that derives phase information from symbols in the packet and a weight that is a function of an estimated power profile for the channel and (2) a computation circuit that computes a weighted average for the phase information using the weight, the weighted average being power profile-based to allow the receiver to detect the data contained in the packet more reliably under the degraded channel conditions.

Abstract: A CSK modulation is applied to transmit input data for transmission by using N PN code series. A modulator for N series synthesizes a predetermined number (n) of PN code series selected from N PN code series in response to m bits in the input data, and the synthesized code series is transmitted onto a transmission medium through a transmitting interface. The PN code series which is actually transmitted has a maximum value of the absolute magnitude of auto-correlation which is always greater than a maximum value of the absolute value of cross-correlations between the remaining synthesized PN code series.