Abstract: A carrier reel according to the present invention is constituted by a flange portion having a first surface and a second surface which is opposed to and substantially parallel to the first surface, and a hub portion which is provided between the first surface arid the second surface and to which the flange portion is connected. A bearing portion at which a shaft used for taking out each electronic component after carriage is supported is provide to the hub portion, and spaces for accommodating therein a drying agent, i.e., drying agent accommodating portions are formed at the part of the hub portion except the bearing portion. The drying agent is accommodated in the drying agent accommodating portions. The carrier reel having the drying agent accommodated therein is put in a damp proof bag to be sealed. The sealed damp proof bag is then packaged to be carried.

Abstract: A method for forming three-dimensional circuitization in a substrate is provided for forming conductive traces and via contacts. In the method, a substrate formed of a substantially insulating material is first provided, grooves and apertures in a top surface of and through the substrate are then formed, followed by filling the grooves and apertures with an electrically conductive material such as a solder. The method can be carried out at a low cost to produce high quality circuit substrates by utilizing an injection molded solder technique or a molten solder screening technique to fill the grooves and the apertures. The grooves and the apertures in the substrate may be formed by a variety of techniques such as chemical etching, physical machining and hot stamping.

Abstract: A method of forming a semiconductor device having a multi-layered wiring structure that includes a conductor layer to be electrically connected to a packaging substrate, with the multi-layered wiring structure being provided on a circuit formation surface of a semiconductor chip. Ball-like terminals are formed, disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side. The multi-layered wiring structure is formed to include a buffer layer for relieving a thermal stress provided between the semiconductor chip and the packaging substrate, due to the packaging procedure. In the semiconductor device formed, the wiring distance is shorter than that of a conventional semiconductor device, so that an inductance component becomes smaller, to thereby increase signal speed.

Abstract: The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (139) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (144) down to a depth lower than the depth of the surrounding field oxide (120), and that the semiconductor structure (144) is then heat treated.

Abstract: In order to isolate a plurality of MOS and bipolar devices provided on the same chip, a plurality of first and second trenches are provided on a semiconductor substrate. Each of the first trenches is filled with silicon oxide containing no impurity and is used to isolate the MOS devices. On the other hand, the second trenches are formed within the first trenches. Each second trench is filled silicon oxide containing phosphorous and boron and is used to isolate the bipolar devices. The inner surface of each second trench is coated with a silicon nitride film for preventing boron (or phosphorous) from being diffused into the surrounding region.

Abstract: An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

Abstract: A method of applying an adhesive material comprising the steps of: providing the adhesive material on an interconnect substrate; and pressure-bonding the adhesive material to the interconnect substrate. A base has a plurality of first regions to be punched out and second regions located between the first regions. An interconnect pattern is formed at least in the first regions. Part of the adhesive material located within the first regions is pressurized to flow toward the second regions to move air bubbles to the second regions.

Abstract: A method of fabricating an integrated circuit including multiple devices and isolation structures separating the multiple devices includes depositing a mask layer with a first thickness above a semiconductor substrate, forming an aperture in the mask, and trimming the mask layer to a second thickness where the second thickness is less than the first thickness.

Abstract: A thick-film conductor, a method for forming the conductor, and a method for attaching a surface-mount circuit device to the conductor with a solder connection. The conductor is formed of a thick-film conductive ink that would normally produce a solderable conductor, but is rendered unsolderable by additions of a fine inorganic particulate material. A solderable region, preferably a pillar, is then selectively formed on the unsolderable conductor to determine the distribution and height of the solder connection on the conductor. In order to suitably affect the solderability of the conductor, the particulate material is present as a fine dispersion and in a sufficient quantity, but not in quantities that significantly affect the electrical, mechanical and processing characteristics of the conductor.

Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.

Abstract: Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.

Abstract: A multi-chip bonding method and apparatus, in which a first wafer ring which has electronic components of a first type is held by a holding device; substrates are fed out to a conveying device from the first storing section; the electronic components of the first type on the holding device are successively bonded to the substrates; the substrates with the electronic components of the first type bonded is accommodated in the second storing section; the first wafer ring held by the holding device is exchanged for a second wafer ring which has electronic components of a second type; the substrates accommodated in the second storing section is fed out to the conveying device; the electronic components of the second type are successively bonded to the substrates; and the substrates with the electronic components of the second type bonded is accommodated in the first storing section.

Abstract: The present invention relates to a chip scale package and a method for providing the same. The chip scale package reduces the length of interconnection through the direct contact of a semiconductor chip and output terminals without a substrate. The chip scale package includes a semiconductor chip in which electronic circuits are integrated, having several bonding pads on an upper side. Output terminals are disposed around the semiconductor chip. Bonding wires connect the bonding pads with the output terminals. The bonding wires and associated components are encapsulated by a molded material, which does not encapsulate the central base of the semiconductor chip and the output terminals.

Abstract: In a package for mounting including a metal plate having a recess portion for mounting a semiconductor chip and a plane portion for mounting a metal pattern layer, the recess portion is thinner than the plane portion.

Abstract: Providing a method of producing a semiconductor device wherein semiconductor element are sealed with a resin by using the same lead and other means regardless of the specifications of the semiconductor elements, and a semiconductor device which can be reduced in size and weight and has good heat dissipation performance and high-frequency performance. The semiconductor devices can be produced by mounting a plurality of the semiconductor elements on the lead frame having leads disposed substantially parallel to each other, sealing the whole with a resin, and cutting off the individual semiconductor devices.

Abstract: A method of fabricating a semiconductor device including preparing a board with a plurality of device carrier areas thereon and an electrode pattern serving as external electrodes on a back of the board. Semiconductor chips are fixed respectively to the device carrier areas. The semiconductor chips fixed to the device carrier areas are covered with a common resin layer. A round surface of the common resin layer is flattened into a flat and horizontal surface, and a dicing sheet is applied to the flat and horizontal surface of the common resin layer with electrode pattern facing upwardly. The board and the common resin layer are separated into segments including the device carrier areas thereby to produce individual semiconductor devices by dicing from the back of the board.

Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

Abstract: In a no-flow underfill process 400, a substrate 10 is heated to an elevated temperature prior to dispensing underfill 5 thereon. The underfill 5 flows more readily over mask portions 20 and conductors 25 on the substrate 10, filling in spaces between the conductors 25 and the masking portions 20, thereby preventing air from being trapped thereabout. In addition, when a bumped die 40 is heated during placement on the substrate 10 with the underfill 5 therebetween, the underfill 5 flows around bumps 45 more readily thereby preventing air from being trapped thereabout. The result is a flip chip semiconductor package having a lower void density.

Abstract: A method and apparatus for encapsulating microelectronic devices. In one embodiment, a microelectronic device is engaged with a support member having a first edge, a second edge opposite the first edge, and an engaging surface with at least a portion of the engaging surface spaced apart from the first and second edges. The first edge of the support member is positioned proximate to a wall of a mold and an aligning member is moved relative to the wall of the mold to contact the engaging surface of the support member and bias the first edge of the support member against the wall of the mold. The microelectronic device is then encapsulated by disposing an encapsulating material in the mold adjacent to the microelectronic device. By biasing the first edge of the support member against the wall of the mold, the method can prevent encapsulating material from passing between the first edge of the support member and the wall of the mold, where the encapsulating material would otherwise form flash.

Abstract: A microelectronic device includes a field oxide isolation pad which extends from a trench formed in a microelectronic substrate by a height which is less than approximately two times the height of a gate structure formed on the microelectronic substrate. Spacers are formed around the gate structures, although little or no spacer forms around the isolation pad.