Abstract: Systems, methods, and other embodiments associated with a backup utility are described. One example system causes a backup utility to identify a remote device as local to a client device. Backup data may then be retained on the remote device identified by the backup utility as being local.

Abstract: Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.

Abstract: In a storage device incorporating a plurality of kinds of disk drives with different interfaces, the controller performs sparing on a disk drive, whose errors that occur during accesses exceed a predetermined number, by swapping it with a spare disk drive that is prepared beforehand.

Abstract: A method and apparatus for selecting a retransmission mode in a MIMO communication system are provided wherein a receiver receives m initial transmission streams from a transmitter, m being an integer of 2 or larger, channel-decodes the m initial transmission streams and checking errors in the m channel-decoded streams, selects, if at least two channel-decoded streams have errors among the m channel-decoded streams, a retransmission mode to be used for the at least two streams having errors in the transmitter, and transmits information including the selected retransmission mode to the transmitter.

Abstract: The invention is intended to curtail the circuit scale of the error correction circuit of a flash memory.

Abstract: A method and apparatus for transmitting control information in a wireless communication system using a Low Density Parity Check (LDPC) code is provided. The number of LDPC blocks, through which L1 post-signaling information is to be transmitted, is determined according to the total number of bits of the L1 post-signaling information. The number of input information bits of each LDPC block is calculated when the determined number of LDPC blocks is plural. The number of puncturing bits among parity bits of each LDPC block is determined considering a modulation order. A frame including one or multiple LDPC blocks generated through the preceding steps is transmitted.

Abstract: A message is generated by a computer operating on a dispersed data storage network indicating the inaccessibility of a plurality of data slices. A rebuilder application operates on the dispersed data storage grid and rebuilds inaccessible data slices, including those identified by the message.

Abstract: A digital broadcasting system for transmitting/receiving a digital broadcasting signal and a data processing method are disclosed. First program table information and second program table information, which has an identifier different from an identifier of the first program information, are multiplexed and transmitted. The first program table information describes main service data through fixed reception channel, while the second program information described mobile service data through mobile reception channel. Thus, a broadcast receiving system can receive and output the mobile service data by parsing the second program table information.

Abstract: A method for decoding an encoded message is described. The method includes obtaining a set of metrics which includes first and second state metrics, and first and second branch metrics. First and second offset values for the iteration are obtained. The first state and branch metrics are added together to obtain a first partial result. The second state and branch metrics are added together to obtain a second partial result. The second partial result is subtracted from the first partial result to obtain a difference. The first partial result and the first offset value are added together to obtain a first result. The second partial result and the second offset value are added together to obtain a second result. Either the first result or the second result is selected for output responsive to the difference. A log correction term is selected responsive to the difference.

Abstract: A digital lighting control network protocol with forward and backward frames, each of the frames including an error check code. A no-acknowledgment (NAK) signal is sent from a receiving node to a transmitting node responsive to the error check code. An interface circuit of the receiving node may include an energy storage section to store at least some energy from the network while receiving digital signals, and an output section to transmit digital signals to the network using the stored energy. The interface circuit may also include a high voltage buffer circuit. The transmitting node may send forward frames to receiving nodes based on device type.

Abstract: An apparatus, program product, and methods for data management, are provided. An exemplary apparatus includes one or more PDHMS surface units each having a serial interface to provide a continuous real-time data stream of captured data, a data storage medium for storing collected downhole process data during a downstream communication link failure, a controller configured to cause the PDHMS surface unit to store recovery data during the downstream communication failure, and a broadband interface to provide recovery file transmission of recovery data stored during the downstream communication link failure. The apparatus can also include a RTU configured to collect the continuous real-time data collected by the PDHMS surface unit and to transmit the collected data to a SCADA system, which can function as a time synchronization master for the RTU and PDHMS surface units, and which can forward the collected data to other systems.

Abstract: An error correction decoder includes a syndrome computation circuit, an error correction and computation circuit and an error correction circuit. The syndrome computation circuit calculates a syndrome of read data. The error correction and computation circuit calculates a location of a single-bit error using a division operation between elements of the syndrome when the single-bit error exists in the read data. The error correction circuit corrects the single-bit error of the read data based on the location of the single-bit error.

Abstract: A semiconductor memory device includes an alignment unit configured to align data received from the outside, a plurality of data input/output lines corresponding to the aligned data, respectively and a realignment unit configured to change correspondence between the data and the data input/output lines in response to one or more change signals in a test mode. A method for testing the semiconductor memory device includes inputting data in series using a testing apparatus, aligning the serial data in parallel, and realigning the parallel data in response to one or more change signals.

Abstract: A Low Density Parity Check (LDPC) encoding apparatus and method are provided. The LDPC encoding apparatus includes a controller for determining a number of zeros b to be inserted in an input information vector when a length of the input information vector is less than a length of a use information vector of a parity-check matrix, for selecting b stopping sets Sd using the parity-check matrix, for selecting one variable node from each of the b stopping sets Sd using a selection scheme, and for determining positions corresponding to the selected variable node from each of the b stopping sets Sd as positions where zeros are to be inserted.

Abstract: Systems and methods for automated determination of error handling. Data is received including one or more procedural operations to be tested. A first test is run on the data to capture one or more first tracebacks, where each traceback is associated with a procedural operation. A determination is made as to whether each captured first traceback is unique, where unique tracebacks are added to a unique traceback list. An error condition is simulated on each unique traceback on the unique traceback list by running a second test. The second test is run once for each unique traceback. One or more second tracebacks are captured during each run of the second test. When a unique traceback being tested matches a captured second traceback, an error code is returned and the second test may be run to completion. Errors encountered during each iteration of the second test running to completion are identified.

Abstract: A first error detection for a first data word is performed using a first error correction code associated with the first data word. In response to the first error detection indicating a first uncorrectable error at the first data word based upon the first error correction code, a second error detection for a plurality of data words including the first data word and a second data word is performed using a second error correction code based upon the first and second data words.

Abstract: Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.

Abstract: A decoding system for use with different degree parity constraint nodes and highly parallel processing operates by passing messages to variable nodes based on updated states of first and second check nodes, processing messages from the variable nodes and updating states of first and second check nodes in a decoder with Z processors that operate in parallel, further processing the updated state information for the second check nodes to coordinate the states of N=Z/z sets of second check nodes, where z is the number of bits associated with the second check nodes, and repeating the process utilizing the coordinated states of the second check nodes as the updated states of the second check nodes.

Abstract: The present invention relates to a method for transmitting a signal in a wireless communication system. The method includes channel coding a data stream using a first turbo encoded puncture pattern, and channel coding the data stream using a second turbo encoded puncture pattern. Preferably, the first turbo encoded puncture pattern is a turbo encoded puncture pattern of a first local operator infrastructure (LOI) and the second turbo encoded puncture pattern is a turbo encoded puncture pattern of a second LOI that neighbors the first LOI.

Abstract: An apparatus, system, and method for providing error protection for data-masking bits in a memory device of a memory system are provided. The memory device includes a memory core to store data, and a data interface to receive the data and data-masking bits associated with a write command. The memory device also includes a gating block to control writing the data to the memory core, where the writing of the data to the memory core is inhibited upon detecting an error with one or more of the data-masking bits.