Abstract: Embodiments disclosed herein describe systems and methods for tuning phases of interface clocks of ASICs in an emulation system for a low latency channel and to avoid read errors. During a bring-up time (e.g., powering up) of the emulation system, one or more training processors may execute a software application to iteratively tune the phases of the interface clocks such that data is written to the interface buffers prior to being read out. To mitigate the problem of higher latency, the training processors may execute software application to tune the clock phases such that there is a small time lag between the writes and reads. The training processors may set the time lag to account for factors such as memory setup and hold, clock skews, clock jitters, and the predicted margin required to account for future clock drift due to carrying operating conditions.

Abstract: A memory device includes a power supply device, a power-on-reset device, a memory array, and a memory controller. The power supply device converts the external supply voltage into an internal supply voltage. When the external supply voltage exceeds a first threshold, the power-on-reset device generates a reset signal. The power-on-reset device further raises the first threshold to a second threshold according to a deep-sleep signal. The memory array is supplied with the internal supply voltage. The memory controller is supplied with the internal supply voltage, accesses the memory array, and is reset according to the reset signal. When the memory controller operates in a deep-sleep mode, the memory controller generates the deep-sleep mode.

Abstract: Applications can be selectively offloaded to ensure that thin clients will have sufficient disk space to install an update. To enable this offloading, a service can be employed to track how long each application is used on the thin client during a particular time period. Based on this usage of each application, the service can assign a rank to each application. The service can also monitor the amount of free space on the disk to determine whether it has fallen below a threshold. If so, the service can employ the ranks to identify applications to be offloaded them by copying an install location folder for each application to a remote repository and then deleting each copied install location folder. When the thin client includes a write filter, the service can commit the deletes of the install location folders so that the applications will remain offloaded after reboot.

Abstract: A method for updating an operating system (OS) comprises: receiving, by an embedded universal integrated circuit card (eUICC), a restart instruction sent by a local profile assistant (LPA) of a terminal device and used to instruct the eUICC to perform a restart operation; sending, to a modem of the terminal device, a first initialization request used to request the modem to control restart of the eUICC; after being restarted, receiving, by the eUICC, a plurality of OS element data packets that are sequentially sent by the LPA; after receiving a part of OS element data packets in the plurality of OS element data packets, parsing, by the eUICC, the OS element data packets received by the eUICC, and installing a first OS based on a parsing result; and deleting, by the eUICC, the first OS element data packet.

Abstract: According to one embodiment, a memory system includes a memory chip and a controller coupled to the memory chip and configured to: instruct the memory chip to execute a write operation in one of a first operation mode and a second operation mode, a program voltage used in the second operation mode being determined on the basis of first information obtained in the first operation mode; manage a power consumption value of the second operation mode on the basis of the first information; and perform power throttling control on the basis of the managed power consumption value.

Abstract: A power control method for controlling power paths between a baseboard and a server board includes: conducting a first power path between the baseboard and a detecting module of the server board via an isolated module; the baseboard obtaining a type of server card of the server board before the server board is powered on; and cutting off the first power path and conducting a second power path between a power source module of the server board and the detecting module of the server board via the isolated module after the server board is powered on; wherein the baseboard provides a side-band signal to the server board.

Abstract: A system and method for message analysis, including: receiving, by a control service, a first modification request to modify a file system of a computing device, wherein the computing device is operating in a read-only state; identifying, by the control service, a request parameter associated with the first modification request; determining, by the control service, that the request parameter satisfies a permission criteria to perform the first modification request; provisioning, by the control service, the computing device to operate in a read/write state in response to determining that the permission criteria has been satisfied, wherein the first modification request is executed to modify the file system while the computing device is operating in the read/write state; and, upon a determination that the first modification request has successfully completed, provisioning, by the control service, the computing device to operate in the read-only state.

Abstract: A method and an apparatus are provided for powering off a portion of a memory of a mobile system. The apparatus may store data within a memory of the apparatus. The apparatus may copy a first portion of the data stored in a first portion of the memory into a second portion of the memory so that the data is stored in the second portion of the memory. The first and the second portion of the memory may be the same memory type. The disclosure discusses various triggering events that may cause the apparatus to copy the first portion of the data stored in the first portion of the memory into the second portion of the memory. The apparatus may then turn off the first portion of the memory. In this manner, the memory consumes less power when storing the data during a low power mode.

Abstract: Modular power delivery techniques for electronic devices are described. In one embodiment, an apparatus may comprise native power delivery circuitry to source a native power delivery current, power management circuitry to control the native power delivery circuitry, a power delivery connector to mate with a counterpart power delivery connector of an external device, and a processing device conductively coupled to the power delivery connector via a supplemental power delivery line, the processing device to draw a supplemental power delivery current from the external device via the supplemental power delivery line. Other embodiments are described and claimed.

Abstract: A method may include, in a chassis configured to provide a common hardware infrastructure to one or more modular information handling systems inserted into the chassis: determining if a save operation is occurring at a time when one or more power supply units are capable of delivering power to the chassis; and delaying power sequencing of the one or more power supply units until the save operation has completed.

Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.

Abstract: A method for determining power dissipation within a computer system is disclosed. A circuit block may receive a regulated voltage level on a power supply signal generated by a voltage regulator circuit. A power control circuit may measure a current drawn by the circuit block, and determine a real-time voltage level for the power supply signal using the current and based on a slope value and a zero-load voltage level. Additionally, power control circuit may determine a power dissipation for the circuit block using the current and the real-time voltage level, and adjust an operation parameter of the circuit block based on the power dissipation.

Abstract: A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.

Abstract: The present application provides a power-down detection circuit and a control method. A low-voltage side power supply is connected to provide an output voltage of the low-voltage side power supply to a power-down detection sub-circuit and provide a standard supply voltage to the power-down detection sub-circuit, a controller and a memory via a voltage conversion circuit. The power-down detection sub-circuit is configured to obtain the output voltage of the low-voltage side power supply, and determine, according to the output voltage of the low-voltage side power supply, whether a power-down event occurs in the low-voltage side power supply. If it is determined that a power-down event occurs, a power-down signal is sent to the controller. The controller receives the power-down signal, and controls the memory to record current information of a high voltage bus sensed by a high-voltage side current sensor.

Abstract: Provided is an information processing device that includes an acquisition unit configured to acquire sensing data and a mode changing unit configured to change a mode on a basis of the sensing data. The acquisition unit changes sensing data to be acquired on a basis of the change of the mode.

Abstract: An image processing apparatus, including a power source, an image engine, an interface to communicate with an external device and deliver power from the power source to the external device, and a controller, is provided. The controller is configured to detect connection of the external device to the interface; receive power information, including a value of regular operable power and a value of minimum operable power, from the external device; receive a job execution command; in response to receiving the job execution command, determine whether a first power value including the value of the regular operable power exceeds a value of power available for the external device during a predetermined operation by the image engine; and in response to a determination that the first power value exceeds the value of power available for the external device, control the power source to deliver the minimum operable power to the external device.

Abstract: An electronic device includes a processor, a volatile memory, and a non-volatile memory. The non-volatile memory stores a first operating system, and the electronic device works in a first working mode and a second working mode. When the electronic device is in the first working mode, a second operating system is run in the volatile memory. When the processor detects that the electronic device reaches a preset condition for entering the second working mode, the non-volatile memory is enabled, and non-system data in the volatile memory is moved to the non-volatile memory. The non-system data does not include the second operating system. After the movement of the non-system data is completed, the volatile memory is disabled, and the first operating system is run in the non-volatile memory, so that the electronic device enters the second working mode.

Abstract: Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.

Abstract: A launch device for launching an electronic apparatus comprises a storage unit, a main storage and a processor. The storage unit is configured to store a mini-launch code for executing a detection of an output value of a sensor, and store system driving codes which comprises a standard launch code for launching electronic apparatus. The main storage loads the mini-launch code and the system driving codes. The processor loads and executes the mini-launch code or the standard launch code.

Abstract: A method and apparatus for managing power in a thermal couple aware system includes determining a candidate configuration mapping based upon one or more criteria, the candidate configuration mapping being a mapping of performance for a candidate configuration of processor sockets in the thermal couple aware system. The candidate configuration mapping is evaluated by comparing the candidate configuration mapping to a stored configuration. If the evaluated candidate configuration mapping provides a better metric than the stored configuration, the stored configuration is updated with the evaluated candidate configuration mapping, and programming instructions are executed in accordance with the candidate configuration mapping if no other configuration mappings are to be determined.