Patents Examined by Joshua P Lottich
  • Patent number: 11544174
    Abstract: Methods and apparatus for protecting trace data of a remote debug session for a computing system. In one embodiment, a method includes storing trace data received from one or more trace interfaces to a storage location of a target device, where the trace data is generated from execution at the target device, and where the trace data is protected from an unauthorized access. The method continues with transmitting the trace data to a debug host computer with encryption through a communication channel between the target device and the debug host computer.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 3, 2023
    Assignee: INTEL CORPORATION
    Inventors: Loren James McConnell, Tsvika Kurts, Boris Dolgunov, Vamsi Krishna Jakkampudi, Marcus Winston, Kevin David Safford
  • Patent number: 11544129
    Abstract: Systems, apparatuses and methods may provide for technology that detects a successful boot of a first firmware component in a computing system, receives a signal from a second firmware component in the computing system, and detects an incompatibility of the first firmware component with respect to the second firmware component based on the signal. In one example, only the first firmware component is repaired in response to the incompatibility.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Janusz Jurski, Mariusz Stepka
  • Patent number: 11537473
    Abstract: The invention discloses a method for controlling other systems based on a single-point execution contract, comprising the following steps: A, when a contract developer writes a single-point execution contract code, integrating a command needing transparent transmission into the code; B, executing, by a virtual machine, the code, calling a transparent-transmission channel command input interface while executing to a row with the command, and transmitting the command to a blockchain node; and C, not processing the command by the blockchain node, and calling a secondary development service package interface through the transparent-transmission command to transmit downwards. In the method, a command transparent-transmission channel and a transparent-transmission command secondary development package service are designed, so that a blockchain user can operate their specific software/hardware equipment through a user-defined command.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: December 27, 2022
    Assignee: SHANGHAI WEIERLIJIE NETWORK TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventor: Wenbin Cheng
  • Patent number: 11526393
    Abstract: A system includes a memory circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. The multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.
    Type: Grant
    Filed: March 14, 2021
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Gerald L. Cadloni, Bruce A. Liikanen, Violante Moschiano
  • Patent number: 11526412
    Abstract: A method includes receiving a plurality of data processing requests and generating a primary processing stack indicating a queue for processing the first data. The primary processing stack comprises a plurality of layers. Each layer comprises a plurality of slices, wherein each slice represents a portion of the first data of at least one data processing request. The plurality of slices are arranged within each layer based at least on the priority indicator corresponding to the first data that each slice represents. The method further includes receiving resource information about a plurality of servers, assigning each slice of the primary processing stack to one of the servers, and sending processing instructions comprising an identification of each slice of the primary processing stack assigned to the respective server.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: December 13, 2022
    Assignee: Bank of America Corporation
    Inventors: Aditya Kulkarni, Rama Venkata S. Kavali, Venugopala Rao Randhi, Lawrence Anthony D'Silva
  • Patent number: 11513942
    Abstract: Systems and methods are disclosed for debug session management. For example, methods may include receiving a request from a client device and, in response, identifying a set of instructions to be executed, wherein the set of instructions is associated with at least one breakpoint. The methods may include initiating execution of the set of instructions. The methods may include determining, based on a marker, that pausing execution of the set of instructions using a data structure is permitted, and responsive to this determination: pausing execution of the set of instructions before executing an instruction associated with a breakpoint, and updating the marker to indicate that execution of the set of instructions has paused using the data structure.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: November 29, 2022
    Assignee: ServiceNow, Inc.
    Inventors: Christopher Tucker, Qian Zhang, Carl David Solis, Jr.
  • Patent number: 11513939
    Abstract: Improved mechanisms and techniques for recording and aggregating trace information from multiple computing modules of a storage system may be provided. On a storage system having multiple computing modules, where each computing module has multiple processing cores, processing cores may record trace information for I/O operations in dedicated local memory—i.e., memory in the same computing module as the processing core that is dedicated to the computing module. One of the processing cores may be configured to aggregate trace information from across multiple computing modules into its dedicated local memory by accessing trace information from the dedicated local memories of the other computing modules in addition to its own. The aggregated information in one dedicated local memory then may be analyzed for functionality and/or performance and additional action taken based on the analysis.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: November 29, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Gabriel Hershkovitz, Jerome J. Cartmell, Arieh Don
  • Patent number: 11500717
    Abstract: Techniques involve: acquiring, through a first downstream port of a first switch of a data storage system, information indicating an error of a storage device array from a second switch of the data storage system, wherein the first switch and the second switch are connected to the storage device array and the first downstream port is connected to a second downstream port of the second switch; executing, based on the acquired information, actual actions intended for solving the error; and in response to the executed actual actions failing to match with expected actions for the error, issuing an alarm indicating failure of processing the error.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: November 15, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Min Zhang, Zhonghua Zhu, Guifeng Tang, Qiulin Cheng, Yechen Huang, Zhenhua Dong, Thomas Dibb
  • Patent number: 11494254
    Abstract: A storage system includes: a control processor, configured to: read user data with a read threshold, determine which threshold adjustment range has been activated by reading a 1 and 0 counter, select an adjusted read threshold, based on the threshold adjustment range, to reread the user data in a physical block using the adjusted read threshold to correct the user data; and reading the user data in the physical block using the adjusted read threshold selected from the threshold adjustment range.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: November 8, 2022
    Assignee: CNEX LABS, Inc.
    Inventors: Jun Tao, Chih-Chieng Cheng, Shanying Luo
  • Patent number: 11481312
    Abstract: Techniques for testing may include: receiving a first command at a framework, wherein the first command includes first information identifying a first test to be executed and a first collector that collects data during execution of the first test; and responsive to receiving the first command, perform processing to execute the first command, wherein the processing is coordinated by the framework and wherein the processing includes: executing the first test; collecting test data, wherein the test data is collected by the first collector during execution of the first test; and generating a report regarding the test data collected while executing the first test.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: October 25, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Brian R. Tetreault, William James Sullivan, Ginamarie E. Spiridigliozzi
  • Patent number: 11474916
    Abstract: Examples include a method of performing failover of in an I/O architecture by allocating a first set of resources, associated with a first port of a physical device, to a virtual device, allocating a second set of resources, associated with a second port of the physical device, to the virtual device, assigning the virtual device to a virtual machine, activating the first set of resources, and transferring data between the virtual machine and the first port using the virtual device and the first set of resources. The method further includes detecting an error in the first set of resources, deactivating the first set of resources and activating the second set of resources, and transferring data between the virtual machine and the second port using the virtual device and the second set of resources.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventors: Mitu Aggarwal, Nrupal Jani, Manasi Deval, Kiran Patil, Parthasarathy Sarangam, Rajesh M. Sankaran, Sanjay K. Kumar, Utkarsh Y. Kakaiya, Philip Lantz, Kun Tian
  • Patent number: 11475126
    Abstract: Systems and methods for modernizing workspace and hardware lifecycle management in an enterprise productivity ecosystem are described.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: October 18, 2022
    Assignee: Dell Products, L.P.
    Inventors: Carlton A. Andrews, Girish S. Dhoble, Nicholas D. Grobelny, David Konetski, Joseph Kozlowski, Ricardo L. Martinez, Charles D. Robison
  • Patent number: 11467949
    Abstract: Mechanisms and techniques for providing an isolated runtime environment are disclosed. Scoped properties are generated utilizing a namespace identifier. The namespace identifier is an identifier used to define a scope of at least an isolated application runtime context. Scoped objects are generated corresponding to one or more dependent services utilizing the one or more scoped properties and the namespace identifier. A target application is deployed to a container corresponding to the isolated application runtime context. The target application interacts with at least some of the dependent services utilizing the namespace identifier. At least one integration test is run on the target application in the container. The integration tests refer to the isolated application runtime context utilizing the namespace identifier.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: October 11, 2022
    Assignee: salesforce.com, inc.
    Inventors: Heng Zhang, Utsavi Benani, Zhidong Ke
  • Patent number: 11467945
    Abstract: Provided herein are systems and methods for resilience testing. A system includes at least one hardware processor coupled to a memory and configured to decode a workflow to obtain a workload specification and a failure experiment specification. A first set of containers is configured to execute one or more workloads on a testing node. The one or more workloads are defined by the workload specification. A second set of containers is configured to execute one or more failure experiments on the testing node. The one or more failure experiments are based on the failure experiment specification. Execution of the one or more failure experiments triggers an error condition on the testing node. A notification is generated based on at least one metric associated with execution of the one or more workloads and the one or more failure experiments.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: October 11, 2022
    Assignee: Snowflake Inc.
    Inventors: Yuchen Cao, Stephen Mark Andrew Clark, Prasanna Kumar Krishnamurthy, Supriya Vasudevan, Jinzhou Yang
  • Patent number: 11461200
    Abstract: Provided is a method, computer program product, and system for performing automated failover and/or failback recovery analysis using predictive analytics. A processor may monitor a disaster recovery (DR) life cycle during a DR scenario. The processor may monitor failover process activities in a DR production environment over a predetermined time period. Based on data collected during monitoring of the DR life cycle and the failover process activities in the DR production environment over the predetermined time period, the processor may generate, using machine learning, a failback blueprint plan to move production to a new production environment.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: October 4, 2022
    Assignee: KYNDRYL, INC.
    Inventors: Joseph Reyes, Hamza Yaswi, Thaddious L. Goodman, Jr.
  • Patent number: 11442798
    Abstract: The present invention discloses a software reliability simulation analysis method based on virtual reality and a complex network, which realizes a two-layer network displaying the coupling of a task network and a function complex network in a virtual reality environment and is convenient for technicians to observe the operation of the network from multiple perspectives. On the basis of a technology of virtual reality, the present invention determines the task simulation based on an operation section, observes the flow of codes and the number of passing through function nodes in real time during the execution of a task, and calculates and assesses the importance degree of the nodes. The task simulation method based on the operation section is more convincing for the assessment of the importance of the nodes.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: September 13, 2022
    Inventors: Shunkun Yang, Minghao Yang, Hongman Li, Xiaodong Gou
  • Patent number: 11429508
    Abstract: A method includes monitoring performance of a generated model while the generated model is being used for classification on live data, the monitoring including determining a first performance value of the generated model at a first point in time and determining a second performance value of the generated model at a second point in time; rendering, within a graphical user interface, a plot including a first axis and a second axis, the first axis including a characterization of a first performance metric and the second axis including a characterization of a second performance metric; and rendering, within the graphical user interface and the plot, a first graphical object at a first location characterizing the first performance value and a second graphical object at a second location characterizing the second performance value. Related apparatus, systems, techniques and articles are also described.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 30, 2022
    Assignee: Aible Inc.
    Inventors: Arijit Sengupta, Jonathan Wray, Grigory Nudelman, Daniel Kane, Geoffrey Grant
  • Patent number: 11422903
    Abstract: Techniques are provided for maintaining and recomputing reference counts in a persistent memory file system of a node. Primary reference counts are maintained for pages within persistent memory of the node. In response to receiving a first operation to link a page into a persistent memory file system of the persistent memory, a primary reference count of the page is incremented before linking the page into the persistent memory file system. In response to receiving a second operation to unlink the page from the persistent memory file system, the page is unlinked from the persistent memory file system before the primary reference count is decremented. Upon the node recovering from a crash, the persistent memory file system is traversed in order to update shadow reference counts for the pages with correct reference count values, which are used to overwrite the primary reference counts with the correct reference count values.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: August 23, 2022
    Assignee: NetApp Inc.
    Inventors: Ananthan Subramanian, Matthew Fontaine Curtis-Maury, Vinay Devadas
  • Patent number: 11416378
    Abstract: An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: August 16, 2022
    Assignee: NXP B.V.
    Inventors: Jan-Peter Schat, Xavier Hours, Andres Barrilado Gonzalez
  • Patent number: 11409617
    Abstract: Various implementations described herein are related to a device having energy harvesting circuitry that experiences power failures. The device may include computing circuitry having a processor coupled to the energy harvesting circuitry. The processor may be configured to reduce a number of write operations to a log structure having a hardware bit-vector used by the computing circuitry to boost computational progress even with the power failures.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 9, 2022
    Assignee: Arm Limited
    Inventors: Emily Kathryn Ruppel, Supreet Jeloka, Parameshwarappa Anand Kumar Savanth, Wei Wang