Abstract: An apparatus, program product and method of processing access requests for a direct access storage device utilize a “fair elevator” algorithm to schedule access requests from a plurality of requesters desiring access to a direct access storage device (DASD). In particular, a fair elevator algorithm arbitrates requests by taking into account both the requesters with which various requests are associated, as well as the relative positions of the data to be accessed on the DASD. By sorting access requests based upon both requester identity and DASD position, both multitasking performance and DASD throughput are improved in a balanced manner, thus improving overall system performance.
Type:
Grant
Filed:
December 7, 1999
Date of Patent:
March 17, 2009
Assignee:
International Business Machines Corporation
Inventors:
Troy David Armstrong, Michael Steven Faunce
Abstract: A method for enabling a data processing system with a host running under an operating system and with a disk array storage device organized by logical devices to processes plural I/O requests from one or more host processors concurrently.
Type:
Grant
Filed:
October 23, 2003
Date of Patent:
January 24, 2006
Assignee:
EMC Corporation
Inventors:
Natan Vishlitzky, Hana Moreshet, Martin Farley, Izhar Sharon, Elizabeth C. Patapoutian
Abstract: A system and method for reducing the number of memory accesses by a hardware device to a descriptor memory is disclosed. Methods, systems and articles of manufacture consistent with the present invention enable software to embed a subsequent descriptor it is posting in the descriptor memory into a current descriptor listed in the descriptor memory. Additionally, hardware is configured to transmit a data packet associated with the current descriptor to a recipient device. When hardware receives an acknowledgment message from the recipient device associated with the transmitted data packet, it fetches the current descriptor to update a completion code within the current descriptor using a Read-Modify-Write (RMW) transfer sequence. As part of the RMW memory operation, hardware may use the embedded copy of the subsequent descriptor within the current descriptor to transmit the next data packet associated with the subsequent descriptor.
Abstract: A method for enabling overlapped input/output requests to a logical device using assigned and parallel access unit control blocks. Each I/O request interrupts an operating system to assign a base and related unit control block to the input/output requests. In addition a parallel access control block is associated with each unit control block for a logical volume and a parallel access main control block is established with a logical volume through which each of the base and related unit control block can be identified. An input/output request to a logical device interrupts the operating system to assign one of the base and one of the assigned unit control blocks to the input/output requests after which control transfers back to the operating system. At a disk storage facility, the input/output request is located in a table with other input/output requests and corresponding parameters.
Type:
Grant
Filed:
October 17, 2003
Date of Patent:
January 4, 2005
Assignee:
EMC Corporation
Inventors:
Natan Vishlitzky, Douglas E. LeCrone, Izhar Sharon, Daniel A. Murphy, William R. Fairchild, Hana Moreshet, Martin Farley, Elizabeth E. Patapoutian
Abstract: Provided are a method, system, and program for handling interrupts. A request is received as to whether a device transmitted an interrupt and a determination is made as to whether the device transmitted the interrupt. If the device transmitted the interrupt, then indication is made that the device did not transmit the interrupt and work from the device related to the interrupt is processed.
Abstract: Disclosed is a method, system, program, and data structure for executing write operations. A first number of write operations is initiated. Performance data is gathered indicating a total time for a second number of the initiated write operations to complete. After at least one initiated write operation has completed, at least one additional write operation is initiated if a number of outstanding write operations is less than a maximum number of write operations. The maximum number of write operations is adjusted if the performance data meets at least one threshold.
Type:
Grant
Filed:
June 9, 2000
Date of Patent:
May 4, 2004
Assignee:
International Business Machines Corporation
Inventors:
David Alan Burton, Robert Louis Morton, Erez Webman
Abstract: A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor and the computer bus. The dynamic buffer allocation system allows simultaneous data transfer from the processor to the buffers, and from the buffers to the computer bus.