Patents Examined by Jositta Jones
  • Patent number: 5863816
    Abstract: A fabrication method for a chip size semiconductor package includes the steps of bonding conductive wires on bonding pads formed on an upper surface of a semiconductor chip, putting the semiconductor chip including the bonded conductive wires in an electrolyzer containing an electrolytic solution in such a manner that one end of each of the conductive wires is exposed outside of the electrolytic solution, attaching a plating electrode to an inner wall of the electrolyzer, attaching a conductive plate to serve as a common electrode to the exposed one end of each of the conductive wires; and connecting the conductive plate and the outer wall of the electrolyzer to an electric current source.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: January 26, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Jae-Weon Cho