Abstract: According to an embodiment of the present invention, a clock synchronization apparatus includes a delay-correcting circuit which is supplied with an initial voltage, compares a phase of an external clock with a phase of an internal clock output from a clock synchronizing unit, generates a control signal for correcting the phase of the internal clock on the basis of a difference between the phases of the external clock and the internal clock, and supplies the control signal to a replica delay unit of the clock synchronizing unit.

Abstract: A memory voltage monitoring circuit generates a low voltage detection signal when a power supply voltage drops below a memory contents holding voltage. A reset circuit generates a reset signal from an external reset signal and outputs the reset signal to the memory voltage monitoring circuit as an operation permission/no-permission signal. The memory voltage monitoring circuit operates while the reset signal shows operation permission.

Abstract: A delay amount variable circuit (8) adapted to change a delay amount according to a ZQ calibration result is inserted in a path of a DQ replica system. The delay amount of the path of the DQ replica system is variable and is adjusted so as to make constant a timing skew difference between a DQ buffer system and the DQ replica system. The ZQ calibration result changes depending on variations in temperature, voltage, and manufacture. Therefore, by obtaining the delay amount corresponding to these variations, there are obtained a DLL circuit with high accuracy that can make the skew difference constant, and a semiconductor device incorporating such a DLL circuit.

Abstract: A low voltage detection circuit includes a reference voltage generation circuit, a divider circuit, a comparator that serves as a comparison circuit, and a second constant current transistor connected in series with the divider circuit. An auxiliary current transistor as well as a first constant current transistor is connected in series with a load element. The auxiliary current transistor is controlled by a voltage at a drain of the second constant current transistor. A gate of the second constant current transistor and a gate of the first constant current transistor are connected with each other to form a current mirror. A size of the second constant current transistor is adjusted so that the second constant current transistor can provide a second constant current that is several times larger than a first constant current provided by the first constant current transistor.