Abstract: A system and method for viewing models and model variables within a sophisticated modeling environment is disclosed. The system provides varying levels of insight into a modeling infrastructure to help the user understand model and model variable dependencies, usage, distribution, and/or the like. The method includes storing model and model variable data within a relational database system, receiving a request from a user interfacing with the system via a web interface, extracting search criteria and presentation preferences from the request, formulating and executing one or more queries on the database to retrieve the required data, formatting the data in accordance with the request, and retuning the data to the requesting user in the form of a web page.

Abstract: A method and apparatus for improving the fatigue life of a wobblefram utilized in a micro switch. The flexible circular wobblefram can be formed with a fixed edge and a solid center region utilizing a punch and die at elevated temperatures. An external lever can be attached to the solid center region of the wobblefram. The lever can be loaded and actuated to transmit motion from outside of the micro switch to a sealed internal mechanism in order to perform a switching function. Circular and/or sinusoidal shaped corrugations can then be added to the wobblefram and evaluated for performance utilizing a finite element analysis (FEA) model. The FEA model can precisely evaluate and optimize profile, number and height of the circular and/or sinusoidal corrugations. Such a wobblefram with circular and/or sinusoidal corrugations can achieve higher lifetime without affecting the operating characteristics of the micro switch.

Abstract: Systems and methods provide for emulating a host architecture in guest firmware. One aspect of the systems and methods comprises determining whether an emulated instruction would cause a transition into a legacy mode. A current execution context is converted into a legacy mode context, and the firmware emulator proceeds to a group of legacy mode instructions in a native mode for the processor. The firmware emulator detects an end instruction and converts the legacy context back to the guest firmware context.

Abstract: To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is easy to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.

Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

Abstract: A system includes a client and an interface component. The client includes (i) a device manager associated with a field device in a process control system and (ii) a first emulator configured to emulate a communication manager. The device manager defines a user interface associated with the field device. The interface component includes (i) a second emulator configured to emulate the device manager and (ii) the communication manager. The communication manager is configured to communicate with the field device over a communication link using a specified protocol. The client is physically separated from the interface component. The communication manager could represent a communication Device Type Manager (DTM), and the device manager could represent a device DTM. Also, the first emulator could emulate at least some functions of the communication DTM, and the second emulator could emulate at least some functions of the device DTM.

Abstract: A method of designing hearing aid molds is disclosed whereby two shapes corresponding to graphical images of ear impressions are registered with each other to facilitate joint processing of the hearing aid design. In a first embodiment, a first graphical representation of a first ear impression is received and a feature, such as the aperture of the ear impression, is identified on that graphical model. A first vector is generated that represents the orientation and shape of that first feature. The three-dimensional translation and rotation of that first vector are determined that are necessary to align the first vector with a second vector representing the orientation and a shape of a feature, once again such as the aperture, of a second ear impression. In another embodiment, this alignment is then refined by minimizing the sum of the distances between points on the first and second graphical representations.

Abstract: A method for simulating an industrial plant includes generating a library of industrial plant component types using user input. The library includes properties of the component types and rules to generate scripts in accordance with property values. The method further includes assembling a configuration of industrial plant components from the library using user input. The configuration is assembled into an editor configured to accept a layout and connection of the configuration of industrial plant components and to accept a configuration and setting of the properties of the industrial plant components. The method also includes generating a script or scripts for industrial plant components in the configuration of industrial plant in accordance with the rules, wherein the generated scripts include mathematical relationships within or among the industrial plant components, or both. The mathematical relationships are then solved. Results are either displayed or used to control an industrial plant.

Abstract: Programming or modeling environments in which programs or models are simulated or executed with tunable sample times are disclosed. The tunable sample times can be changed during the simulation or execution of the programs or models without recompiling the programs or models. The sample times are parameterized and the value of the sample times is changed during the simulation or execution of the programs or models. The sample times may be changed manually by a user. Alternatively, the sample times may be automatically changed by programmatically defining when and how the sample times are determined.

Abstract: A timing analysis apparatus has a block simulation information storing section, a SPICE deck generating section, and a feedback-based static timing analyzing section. The block simulation information storing section stores simulation information for each block when performing circuit analysis by partitioning a circuit into blocks, the SPICE deck generating section generates a SPICE deck by interconnecting the blocks, for a path that needs analysis, by using a result of static timing analysis and using simulation conditions for the each block. The feedback-based static timing analyzing section causes a result of the simulation performed using the generated SPICE deck to be reflected in the static timing analysis.

Abstract: This invention features an FPGA emulation system including an FPGA device under test having a plurality of pins. A bus functional model circuit responsive to signals representing predetermined input characteristics of the FPGA device under test and configured to apply one or more signals to the FPGA device under test corresponding to the predetermined input characteristics and configured to receive one or more signals representing output characteristics of the FPGA device under test to emulate the operation of the FPGA device under test in a predefined selectable and flexible electrical operating environment.

Abstract: A method of optimising a sequential combinatorial process comprising an interchangeable sequence of events uses a master model to model a selection of the possible sequences. Information derived from the master model is used in a surrogate model that approximates the master model. The surrogate model calculates all possible sequences using an algorithm to select information calculated by the master model that most closely matches the events of a present sequence, following a prioritised system so that the best match is used wherever possible. All results from the surrogate model are compared to identify the modelled sequence that gives results closest to a desired optimum result.

Abstract: A method identifying apertures of ear impressions is disclosed. A plurality of contour lines associated with an ear impression are determined and a difference value between a value of a characteristic, such as the diameter, of each contour line and that characteristic of an adjacent contour line is determined. The aperture is identified as being that contour line having the greatest difference value. The contour lines are determined by identifying where a plane intersects the surface of the graphical representations. In another embodiment, the contour lines are assigned a weight. A contour index is then calculated for each contour line as a function of the difference value and these weights. According to this embodiment, the aperture is identified as being a contour line that is adjacent to that contour line having the greatest contour index.

Abstract: Models are generated using a variety of tools and features of a model generation platform. For example, in connection with a project in which a user generates a predictive model based on historical data about a system being modeled, the user is provided through a graphical user interface a structured sequence of model generation activities to be followed, the sequence including dimension reduction, model generation, model process validation, and model re-generation. Historical multi-dimensional data is received representing multiple variables transformed to be maximally predictive for at least one outcome variable to be used as an input to a predictive model of a commercial system, model development process is validated for at one or more sets of such variables and enabling a user of a model generation tool to combine at least two of the variables from the sets of variables.

Abstract: A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a “sink” state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

Abstract: A software-based development tool is operative to automatically determine an appropriate simulation configuration for a multistage switch fabric or other multiple circuit element electronic system. The development tool includes an interface permitting user control of one or more configurable parameters of the electronic system, and automatically generates a simulation configuration for the electronic system based on current values of the configurable parameters. The simulation configuration is advantageously generated without requiring further user input, and specifies interconnections between the circuit elements which satisfy the current values of the configurable parameters.

Abstract: A method for registering two three-dimensional shapes is disclosed whereby the two shapes are represented as zero level set of signed distance functions and the energy between these two functions is minimized. In a first embodiment, two undetailed ear impression models are rigidly registered with each other. In another embodiment, a detailed ear impression is initially aligned with an undetailed ear impression model and, then, the detailed ear impression model is rigidly registered with the undetailed ear impression model as a function of the signed distance functions. In accordance with another embodiment, an undetailed ear impression model is non-rigidly registered with a template ear impression model as a function of the signed distance functions.

Abstract: A simulation method designs an aperture to obtain optimum resolution and DOF in consideration of the layout of a circuit pattern of a photomask, and a recording medium in which the simulation method is recorded. The simulation method for designing an aperture in an exposure apparatus including a light source, an optical lens group, a photomask, an aperture, receives the layout information of the photomask. The aperture is divided into a plurality of pixels. The pixels of the aperture are flipped, a photolithography simulation is executed to produce a simulated photoresist pattern, and the shape of the aperture that provides an optimum resolution for the simulated photoresist pattern is searched for. Beneficially, a system is provided to execute the method. Also, beneficially, the simulation method may be stored on a storage medium.

Abstract: Simulation of models within a distributed environment is facilitated. A model is partitioned based on clock domains, and communication between partitions on different processors is performed on synchronous clock boundaries. Further, data is exchanged across the network on latch boundaries. Thus, management aspects of the simulation, such as management associated with the global simulation time, are simplified.

Abstract: A method of providing ad hoc verification for a simulation includes generating a cumulative record of a state value for the simulation of a circuit design, comparing the cumulative record of the state value to a golden record of the state value to obtain a comparison result, and performing ad hoc verification of the circuit design using the comparison result.