Abstract: A disclosed system includes a central processing unit (CPU), a system memory, an embedded controller (EC) and an encoder. The encoder is configured to receive a multi-bit indicator associated with a hardware resource and generate an analog signal indicative of the indicator. The EC is configured to receive and process the analog signal to obtain the indicator and to perform an action determined based on the indicator. The EC may include programmable I/O pins including one or more analog-to-digital converter (ADC) pins. In at least one embodiment, a single ADC pin of the EC is used to receive the analog signal. In at least one embodiment, the multi-bit indicator includes a minimum of three and a maximum of five bits. In these embodiments, the single pin of the EC is able to resolve 8 to 32 different values of the multi-bit indicator.

Abstract: Buses such as USB4 or Thunderbolt 4 buses may allow for device combinations that actually cannot be accommodated on the bus. A monitoring component, e.g., software and/or hardware component, such as an Operating System (OS) policy manager, may monitor a bus for events identifying changes to devices on the bus. The monitoring component may influence mode changes to hardware/software, such as to the USB configuration, device driver settings, attached device settings, and/or settings for devices attaching to the bus. Influenced changes facilitate accommodating changes to the devices attached to the bus. For example, if a display is attached and it would exceed available bus bandwidth, cause an excess system load, or cause some other problem, rather than fail to enumerate the display, instead hardware and/or software associated with the bus may be influenced to result in a resolution reduction for the display to accommodate it attaching to the bus.

Abstract: A controller capable of preparing capability information for an interconnection protocol and an electronic device are provided. The controller is for a first device linkable to a second device according to the interconnection protocol. The controller includes a hardware protocol engine and a processing unit. The hardware protocol engine is for implementing a link layer of the interconnection protocol, and capable of performing capability extraction and frame formatting to output capability frame information to a data buffer region and capable of sending, according to content of the data buffer region, a capability frame to the second device during Link Startup Sequence (LSS) capability exchange for the interconnection protocol. The processing unit is configured to be capable of modifying, during the LSS capability exchange, the content of the data buffer region after the capability frame information is output to the data buffer region and before the capability frame is sent to the second device.

Abstract: A storage device connected to an information processing apparatus includes processing circuitry configured to perform data transfer with the information processing apparatus at any one of a plurality of predetermined data transfer rates. The processing circuitry is further configured to perform the data transfer with the information processing apparatus at a data transfer rate lower than a data transfer rate of an upper limit among the plurality of data transfer rates, without performing the data transfer at the data transfer rate of the upper limit.

Abstract: An input buffer includes a pair of input transistors and associated injection circuits. A first input transistor has a source coupled to a first voltage rail through a first current source and a gate coupled to a first wire of a multi-wire serial bus. Three or more resistors in a first injection circuit couple the wires of the serial bus to a first common node, which is coupled to the source of the first input transistor by a first capacitor. A second input transistor has a source coupled to the first voltage rail through a second current source and a gate coupled to a second wire of the serial bus. Three or more resistors in a second injection circuit couple the wires of the multi-wire serial bus to a second common node, which is coupled to the source of the second input transistor by a second capacitor.

Abstract: A modular IoT sensor system for Internet of things includes a network module and an expanded sensor module. The expanded sensor module includes a male connector and a female connector respectively disposed in two connection surfaces of the expanded sensor module, configured to detachably connect to a female connector of the network module. Shape and size of the female connector of the network module and the male connector and the female connector of the expanded sensor module conform to a USB type-C specification and pin definitions thereof are complied with a first pin definition different from USB type-C specification.

Abstract: A high-speed scalable backplane enables communications between a central processing unit (CPU) module and field input/output (I/O) and/or communication modules. The backplane comprises a root hub associated with the CPU module. The backplane also includes a plurality of Universal Serial Bus (USB) hubs sequentially coupled to each other and arranged according to the tiered architecture. Each of the USB hubs has an upstream port and a plurality of downstream ports. A top USB hub has an upstream port coupled to a host port of the root hub. One or more lower USB hubs each have an upstream port coupled to a selected downstream port of one of the USB hubs in an immediately preceding tier of the tiered architecture. The lower USB hubs are each configured to enable a plurality of I/O and/or communications connections for the modules via a plurality of downstream ports.

Abstract: An apparatus includes components, a distributed timebase circuit, an interface and a Time Synchronization Circuit (TSC). The timebase circuit is configured to provide local timebases in physical proximity to the components, and synchronize the local timebases to a global timebase so as to provide a consistent time measurement. The interface is configured to be coupled to one or more devices. Transmissions on the interface are logically divided into a plurality of frames. Time on the interface is defined based on a frame number identifying a particular frame. The TSC is configured to capture a first timestamp based on the frame number corresponding to a point in time on the interface, and to concurrently capture a second timestamp based on a local timebase corresponding to the point in time, wherein the first timestamp and the second timestamp correlate time on the interface to the consistent time measurement.

Abstract: The disclosed techniques store certain information of functional modules and lanes to optimize a die-to-die interconnect link. Based on the information, the apparatus can optimize a link width and a multi-module link configuration of the interconnect link. An integrated circuit device includes a first die, a second die, and a die-to-die (D2D) interconnect link connected between the first die and the second die. The D2D interconnect link includes a plurality of lanes grouped into a plurality of modules. The apparatus maintains a training result of the D2D interconnect link based on the training of the D2D interconnect link, the training result including one or more link configurations of the plurality of modules. The apparatus selects a link configuration of the one or more link configurations to configure the D2D interconnect link including one or more of the plurality of modules.

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to enumerate respective sideband addresses to ten or more memory devices, and provide bi-directional communication with an individual memory device of the ten or more memory devices with a particular sideband address enumerated to the individual memory device. Other embodiments are disclosed and claimed.

Abstract: A board mis-insertion prevention circuit includes a first detection circuit, a second detection circuit, and a control module. The first detection circuit detects whether a board is in a first state and outputs a first detection signal when the board is in the first state. The second detection circuit detects whether the board is in a second state when the board is not in the first state, and outputs a second detection signal when the board is in the second state. The control module receives the first detection signal or the second detection signal and can allow or disconnect a power supply to the board according to the first detection signal or the second detection signal.

Abstract: A synchronization optimization method for EtherCAT master slaves is provided. By capturing a time when a master sends a data frame, a time when receives, and a time when a reference slave receives the data frame, a transmission delay is calculated. A compensated transmission delay is obtained. A time taken for a data frame to leave a parent port and return to the same parent port, a transmission delay, a clock offset, and a clock drift are calculated. The clock drift is compensated. A new clock offset is obtained by subtracting the compensated clock drift from the clock offset and written into the non-reference slave for compensation to complete a synchronization optimization. The present application reduces the clock drift and enables the master to compensate for the clock drift of each slave more rapidly.

Abstract: A vehicle-mounted information processing apparatus is mounted in a vehicle and includes: a plurality of processing units that perform processing in parallel or pseudo-parallel; a shared storage unit that is accessible by the plurality of processing units; and a detection unit that detects an abnormality at the shared storage unit. The processing units each include a communication unit that performs communication via a communication line, and the plurality of processing units exchange information via the shared storage unit. When the detection unit has detected an abnormality at the shared storage unit, the processing units exchange information through communication using the communication units. The plurality of processing units and the shared storage unit may be integrated into a single integrated circuit, and information may be exchanged via a communication line outside the integrated circuit when the detection unit has detected an abnormality at the shared storage unit.

Abstract: A computer-implemented method for processing data which are associated for example with a signal transmittable and/or transmitted via a bus system, for example of a vehicle, including: at least intermittent provision of reference data for a statistical model which characterizes at least one average of at least one characteristic of the signal on the basis of a first average determined, for example dynamically, over a predefinable unweighted first number of values for the characteristic, and at least intermittent modification of the reference data at least in part on the basis of a second average determined, for example dynamically, over a predefinable weighted second number of values for the characteristic.

Abstract: In some examples, a management controller is to dynamically vary a parameter that controls an operational characteristic of a bus when transferring different portions of information from a memory over the bus during a process of an electronic device in which a cryptographic operation is performed. The different portions of the information from the memory are to be transferred over the bus with different operational characteristics of the bus.

Abstract: Apparatuses and methods for enabling an MFi stack and corresponding MFi application to be authenticated in an emulator operating using one or more processors/CPUs are presented. In one aspect, a computer may include a memory and processor configured to execute the operating system. The computer may include a USB bus coupled through USB interface to a dongle. The dongle may include an authentication coprocessor for use in an integrated circuit (I2C)-to-USB configuration, and an I2C-to-USB computer. Driver code running on the computer may manage the data exchanged between the authentication coprocessor and a virtual emulator on the computer. The emulator may include a USB-to-I2C driver that virtualizes the authentication coprocessor as an I2C device running with the MFi application like CarPlay.

Abstract: A system for transmitting data based on serial communication, which allows the number of slave apparatuses connectable to one master apparatus to be increased, includes a master apparatus configured to generate an input data packet including first data, second data, and control data, and a slave apparatus group consisting of a plurality of slave apparatuses connected in a daisy-chain manner to the master apparatus, wherein each of the slave apparatuses determines first identification information (ID) using bits included in the first data, extracts second ID from the second data, and controls a target device using the control data when the first ID and the second ID match.

Abstract: An information processing device includes a computer system and a dedicated device connected via a dedicated bus, wherein the computer system implements a monitoring unit via an operating system thereof. The monitoring unit includes a detection module configured to detect the blocked state of the dedicated bus, and a blocking release module activated upon detecting the blocked state of the dedicated bus and configured to perform a blocking release process for instructing the operating system to disconnect the dedicated device, for releasing the blocked state of the dedicated bus, for instructing the operating system to reset the dedicated device disconnected from the computer system, and for instructing the operating system to reconnect the dedicated device to the computer system after resetting the dedicated device.

Abstract: An attachment device is provided for Ethernet communication to a radio. The device includes a transmit/receive circuit, an interface for universal serial bus (USB)-to-Ethernet, an oscillator, a supervisor circuit, a programmable read-only-memory (PROM), a current regulator, a printed circuit board and a housing. The transmit/receive circuit receives a communication signal via an RJ45 receptor from Ethernet. The USB-to-Ethernet interface connects to the RJ45 receptor to forward the communication signal to the USB. The host connector receives the communication signal from the USB for forwarding to the radio. The oscillator provides a periodic clock signal. The three-pin microprocessor supervisor circuit sequences the communication signal via the clock signal and sequence protocol. The PROM buffers the communication signal and the sequence protocol. The current regulator restricts voltage range of the supervisor circuit. The interface, oscillator, supervisor circuit, PROM and current regulator mount to the PCB.

Abstract: Systems and methods of communicating use device level throttling. Some embodiments relate to a method of communicating in a network. The systems and methods can provide a first communication associated with a device for issuance, issue the first communication if a queue depth value for the device is less than an issued communication value, and listing the first communication on a pend list for the device if a queue depth value for the device is less than the issued communication value.