Patents Examined by Jue Wang
  • Patent number: 8631389
    Abstract: Techniques for authenticating one or more configuration items in an information repository are provided comprising the step of running an audit on the one or more configuration items in accordance with a change history of each of the one or more configuration items and one or more request for change identifiers.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Glenn C. Aikens, Melissa Jane Buco, Maheswaran Surendra, Christopher Ward, Steve Weinberger, Sam Shixiong Yang
  • Patent number: 8621449
    Abstract: There is provided an autonomic software system and method for normalizing a profile collected for an executing application to account for one or more actions applied to the executing application after the profile was collected, comprising: predicting an impact of applying the one or more actions to the executing application by utilizing the profile and the one or more actions; and adjusting the profile to form a normalized profile according to the predicted impact. A plurality of different a profile consumers, such as, a phase shift detector, an action evaluator as well as a normalizing controller, may utilize the normalized profile to improve the behavior of the executing application. In addition, online visualization tools may be implemented to graphically depict the normalized profiles, as well as differences between the collected profiles and the normalized profiles.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Hind, Peter F. Sweeney
  • Patent number: 8621444
    Abstract: Methods for simulating an instruction set architecture (ISA) with a instruction set simulator (ISS) are provided. One exemplary embodiment of the methods includes fetching a first decoded instruction during a run time, where the decoded instruction is decoded from an original instruction in a target application program during a compile time preceding the run time. The decoded instruction can designate a template configured to implement the functionality of the original instruction. The method also preferably includes determining whether the fetched instruction is modified from the original instruction and then executing the designated template if the instruction was not modified. The method can also include decoding the original instruction during the compile time by selecting a template corresponding to the original instruction and then customizing the template based on the data in original instruction. The method can also include optimizing the customized template during the compile time.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: December 31, 2013
    Assignee: The Regents of the University of California
    Inventors: Nikil Dutt, Mohammad H. Reshadi
  • Patent number: 8612955
    Abstract: A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: December 17, 2013
    Assignee: University of Washington
    Inventors: Mark H. Oskin, Steven J. Swanson, Susan J. Eggers
  • Patent number: 8612960
    Abstract: Embodiments include a system for loading components with complex intra-dependencies. Components in the system may be assigned at start up to a common loader module. The system detects reference cycles amongst the set of components in the system. All components in a reference cycle may be assigned for loading to the same common loader. This system avoids deadlock scenarios by identifying reference cycles at start up and assigning each cycle to a single common loader. The embodiments of the system also analyze components to be loaded that are identified after start up to determine if they cause a new reference cycle. Components that cause a new reference cycle may not be allowed to be loaded to prevent deadlock loading scenarios.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: December 17, 2013
    Assignee: SAP AG
    Inventors: Petio G. Petev, Nikolai S. Dimitrov
  • Patent number: 8589882
    Abstract: A method that may include: monitoring over time, actions carried out by at least one programmer over a software development environment to yield development patterns; comparing the development patterns to best practice rules to yield a comparison results indicating deviations of the development patterns from the best practice rules; and analyzing the comparison results based at least partially on a likelihood of each action deviated from the respective best practice rule to result in a software bug, to yield an analysis of potential software bug prone code sections, wherein at least one of the monitoring, the comparing, and the analyzing is executed by at least one processor.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Moran Shochat, Itzhack Goldberg, Aviad Zlotnick, Shmuel Ur
  • Patent number: 8572578
    Abstract: The present invention extends to methods, systems, and computer program products for script debugging. Embodiments of the invention serve as a plug-in to an existing debugger. The plug-in leverages the debugger's user-interface and engine. The plug-in can be a controller that subscribes to common notifications and is guided by a state machine, which stitches together a script control channel with an existing debug channel.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: October 29, 2013
    Assignee: Microsoft Corporation
    Inventor: Jonathon Michael Stall
  • Patent number: 8549501
    Abstract: Generating mixed-mode operations in the compilation of program code for processors having vector or SIMD processing units is disclosed. In a preferred embodiment of the present invention, program instructions making up the body of a loop are abstracted into virtual vector instructions. These virtual vector instructions are treated, for initial code optimization purposes, as vector instructions (i.e., instructions written for the vector unit). The virtual vector instructions are eventually expanded into native code for the target processor, at which time a determination is made for each virtual vector instruction as to whether to expand the virtual vector instruction into native vector instructions, into native scalar instructions, into calls to pre-defined library functions, or into a combination of these. A cost model is used to determine the optimal choice of expansion based on hardware/software constraints, performance costs/benefits, and other criteria.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Alexandre E. Eichenberger, Kai-Ting Amy Wang, Peng Wu
  • Patent number: 8539467
    Abstract: Embodiments relate to solving conflicts in assembler programs. An aspect includes generating an internal representation of the control flow of the source code of the assembler program, the internal representation including nodes for every instruction and a directed edge for every possible flow of control between nodes. Data attributes are attributed to the nodes and/or the edges to store the information about whether the resource used by an instruction is available or for which amount of time is unavailable. A data-flow analysis is the applied to the internal representation of the control flow of the source code to determine whether the resource used by an instruction of the assembler program is available or for which amount of time is unavailable. Each node is checked for whether the instruction accesses a resource which is unavailable. An appropriate action is then taken to overcome the resource conflict.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventor: Wolfgang Gellerich
  • Patent number: 8516462
    Abstract: A computer implemented method, apparatus, and computer usable program code for monitoring and managing a stack. Usage of stack space is monitored for a plurality of threads. Usage of stack space is compared to a policy to form a comparison. An action is selectively initiated based on the comparison to the policy.
    Type: Grant
    Filed: October 9, 2006
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jimmie Earl DeWitt, Jr., Riaz Y. Hussain, Frank Eliot Levine
  • Patent number: 8473934
    Abstract: In one aspect, there is a formalized method for mapping applications on a multiprocessor system. In particular re-use possibilities are explored, e.g. focus on data transfer and memory access issues, with the aim of obtaining low-power and low-energy mappings and/or to overcome memory performance or energy bottlenecks.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: June 25, 2013
    Assignee: IMEC
    Inventors: Erik Brockmeyer, Tanja Van Achteren
  • Patent number: 8458673
    Abstract: A computer-implemented method and system for binding digital rights management executable code to a software application are disclosed. The method and system include selecting a memory page of host application code, translating the contents of the selected memory page of host application code, saving the translated contents of the selected memory page into a stub code area, overwriting the selected memory page of host application code; removing host page permission for execution of code in the selected memory page of host application code, and emulating the translated contents of the selected memory page when an exception is raised as a result of attempted access to the selected memory page of host application code.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: June 4, 2013
    Assignee: Flexera Software LLC
    Inventors: Ivan Gadea, Andres M. Torrubia
  • Patent number: 8448126
    Abstract: This invention provides a compliance assessment system and tool for efficiently assessing compliance programs and managing compliance program assessments across an organization. Compliance activities are measured against a group of Compliance Program Element Requirements (CPR's) that are used to assess LOB compliance programs. The CPR's define the minimum standards for the LOB's documentation and execution of its compliance program. Assessment results are documented and a compliance program assessment data sheet is developed. A rating is also provided for the status of the documentation supporting the compliance program and the effectiveness of the execution of the compliance program. From these inputs the tool of the invention automatically calculates a score representative of the adequacy and effectiveness of the compliance program. The tool also assigns a color code based at least in part on the score. Reports may be generated that can be used to determine compliance trends.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: May 21, 2013
    Assignee: Bank of America Corporation
    Inventors: Kimberly Laight, Jennifer G. Ackerman, Burl Edwin Allen, Jr., Anita W. Sabol, Dennis J. McInerney, Janine D. Thomas
  • Patent number: 8429612
    Abstract: Reducing graphical user interface (GUI) noise maybe achieved by recording a first execution scenario for control of operation of an application program having a GUI during a recording phase of operation of a cognitive control framework system, setting soft conditions for a search for the application program for the first execution scenario, playing back the application program according to the first execution scenario during a playback phase of operation of the cognitive control framework system, updating the first execution scenario to form a second execution scenario to reduce GUI noise conditions observed during playback, including updating recorded images originally generated by the GUI during the recording phase and updating coordinates for user input data, setting stronger conditions for the search for use in subsequent playbacks; and playing back the application program according to the second execution scenario with the stronger conditions for search.
    Type: Grant
    Filed: November 11, 2005
    Date of Patent: April 23, 2013
    Assignee: Intel Corporation
    Inventor: Denis Sergeevich Milov
  • Patent number: 8418129
    Abstract: A method is provided for automatically generating code to define and control a system of connected hardware elements. The method comprises: accepting a system configuration macro with sub-macros for system elements, subsystem elements, and connections there between; accepting a plurality of tables with a plurality of system element behaviors, a plurality of subsystem element behaviors, and a plurality of connection options; defining the system of connected elements in response to selecting sub-macros; defining the physical links between the system elements and the behavior of the system and subsystem elements in response to populating the selected sub-macro parameters; expanding the selected sub-macros; generating executable code; and, accessing the tables in response to parameters in the executable code. Advantageously, the form and function of the system can be defined with programming, or writing application specific code.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: April 9, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Alberto Alessandro Della Ripa, Peter Benschop, Philip Michael Clovis, Peter Mark Bouvier, Steven Dean Michel, David Dvorman, Diego Escobar
  • Patent number: 8387029
    Abstract: A method for parsing and executing a software program includes receiving a portion of a software program in an original linguistic form, wherein the portion of the software program includes a nonlinear program element having a body, and, while retaining the original linguistic form, directly executing the nonlinear program element by manipulating a parse state and an input stream of tokens representing the body of the nonlinear program element, wherein directly executing comprises executing tokens until the dynamic end of the nonlinear program element is reached. A system includes a tokenizer operable to tokenize the software program and a parser operable to directly execute a nonlinear program element in the software program by manipulating a parse state and an input stream of tokens representing the body of the nonlinear program element, while preserving the original linguistic form of the software program.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: February 26, 2013
    Assignee: Hercules Software, LLC
    Inventor: Peter L. Bird
  • Patent number: 8381203
    Abstract: A compiler is configured to determine a set of points in a flow graph for a software program where multithreaded execution synchronization points are inserted to synchronize divergent threads for SIMD processing. MIMD execution of divergent threads is allowed and execution of the divergent threads proceeds until a synchronization point is reached. When all of the threads reach the synchronization point, synchronous execution resumes. The synchronization points are needed to ensure proper execution of the certain instructions that require synchronous execution as defined in some graphics APIs and when synchronous execution improves performance based on a SIMD architecture.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: February 19, 2013
    Assignee: NVIDIA Corporation
    Inventors: Boris Beylin, Robert Steven Glanville
  • Patent number: 8375375
    Abstract: A method and system of auto parallelization of zero-trip loops that substitutes a nested basic linear induction variable by exploiting a parallelizing compiler is provided. Provided is a use of a max{0,N} variable for loop iterations in case of no information is known about the value of N, for a typical loop iterating from 1 to N, in which N is the loop invariant. For the nested basic induction variables, an induction variable substitution process is applied to the nested loops starting from the innermost loop to the outermost one. Then a removal of the max operator afterwards through a copy propagation pass of the IBM compiler is provided. In doing so, the loop dependency on the induction variable is eliminated and an opportunity for a parallelizing compiler to parallel the outermost loop is provided.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: February 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Zhixing Ren, Raul Esteban Silvera, Guansong Zhang
  • Patent number: 8359579
    Abstract: A method for generating one or more satisfaction records for an expression in a software application, the expression including at least one criterion relating to the application wherein the satisfaction of the criterion can be determined only at application execution time, the method comprising: analyzing the application to generate a first set of locations in the application where the at least one criterion is potentially satisfied; executing the application; monitoring the application to generate a second set of locations in the application where the at least one criterion is actually satisfied; for each location in the second set of locations generating a satisfaction record indicating that the application satisfied the at least one criterion at the location; and for each location in the first set not in the second set generating a satisfaction record indicating that the application did not satisfy the at least one criterion at the location.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: January 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Matthew Paul Chapman, Adrian Mark Colyer, Benjamin John Dalziel
  • Patent number: 8356291
    Abstract: There is provided an autonomic software system and method for normalizing a profile collected for an executing application to account for one or more actions applied to the executing application after the profile was collected, comprising: predicting an impact of applying the one or more actions to the executing application by utilizing the profile and the one or more actions; and adjusting the profile to form a normalized profile according to the predicted impact. A plurality of different a profile consumers, such as, a phase shift detector, an action evaluator as well as a normalizing controller, may utilize the normalized profile to improve the behavior of the executing application. In addition, online visualization tools may be implemented to graphically depict the normalized profiles, as well as differences between the collected profiles and the normalized profiles.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Hind, Peter F. Sweeney