Abstract: Described are methods and devices for processing a signal transmitting symbols which are temporally spaced on symbol intervals. The signal may be tapped at fractional symbol intervals to provide a plurality of signal taps at the fractional symbol intervals. Each of a plurality of coefficients may be applied to a corresponding one of the signal taps to generate an equalized signal. For at least one of the signal taps, the corresponding coefficient may be updated no more frequently than once per symbol interval.

Abstract: A method for compensating for attenuation in an input signal includes receiving an input signal, communicating a first portion of the input signal on a first path, communicating a second portion of the input signal on a second path, and communicating a third portion of the input signal on a third path. The method also includes applying a first gain to the first portion of the input signal, applying a first-order mathematical operation and a second gain to the second portion of the input signal, and applying a second-order mathematical operation and a third gain to the portion of the input signal. The method further includes recombining the first portion, the second portion, and the third portion into an output signal.

Abstract: Disclosed is a method for generating a space-time trellis code (STTC) for maximizing space-time diversity gain and coding gain in a mobile communication system including at least two transmission antennas and generating a second number of STTC codes with an information data bit stream upon receiving the information data bit stream comprised of a first number of bits.

Abstract: A feed forward equalizer for analog equalization of a data signal received over a data transmission channel comprising a Master Delay Locked Loop (MDLL) for generating equidistant reference phase signals; a Slave Delay Line (SDL) formed by serial connected Slave Delay Units (SDU), wherein each Slave Delay Unit (SDU) has a Slave Delay Element (SDE) to delay the received data signal with a predetermined delay time (?T) and an analog amplifier which amplifies the delayed output signal of the Slave Delay Element (SDE) with a respective weighting coefficient to generate a weighted delay signal, wherein the analog amplifier is switched transparent in response to a corresponding reference phase signal generated by said Master Delay Locked Loop (M-DLL); and subtracting means for subtracting the weighted delay signals which are selected by means of a multiplexer from the received data signal to generate an equalized output data signal.

Abstract: Within a synchronization stage, m candidates are selected according to secondary correlation results that are generated in a standard code group and slot number identification process. Each candidate contains a respective code group number and slot number, and m is greater than 1. A primary scrambling code correlation process is performed with each candidate to obtain a corresponding primary correlation result for an associated primary scrambling code number. The primary scrambling code correlation process for each candidate is performed over x slots, where x is determined by the ratio f/m, f being the number of slots per frame, and x being less than f. Within integer constraints, x is ideally f/m. The respective code group number, slot number and primary scrambling code number of the candidate having the greatest primary correlation result are then selected as a synchronization result.

Abstract: A device for performing predetermined processing on an input signal that may have a signal amplitude of more than one bit. The input signal is obtained by subjecting one-bit serial signals to predetermined signal processing, wherein the signal amplitude of more than one bit is converted to a one-bit serial signal by accumulating the signal amplitudes that exceed one bit, delaying the accumulated signal on the basis of the input signal, and outputting the accumulated signal.

Abstract: Although DC offset reduction schemes can be applied in the analog domain, the residual static DCO in baseband is still present, significantly influencing the performance of high-level modulation schemes employed by recent high-data-rate wireless communications standards. In order to achieve satisfactory performance, DCO compensation algorithms are required in the digital domain. One such algorithm was developed which is based on joint estimation of the Channel Impulse Response (CIR) and the static DCO and ensures satisfactory performance of EDGE modem with direct conversion radio architectures. A further modification of the joint estimation algorithm, the so-called “perturbed joint L”, results in further improvement in the performance of the EDGE equalizer in critical fading channels.

Abstract: A robust timing offset compensation scheme for multi-carrier systems. According to the invention, a timing offset compensator is provided to compensate a current symbol in the frequency domain for the effect of timing offset with a timing offset prediction value. Then a timing error estimator calculates a timing error value for the current symbol based on a function of a phase tracking value, a channel response of each pilot subcarrier, transmitted data on each pilot subcarrier, and a timing compensated version of the current symbol on the pilot subcarrier locations. Furthermore, a timing tracking unit receives the timing error value of the current symbol to generate a shift amount of the DFT window and the timing offset prediction value for a next symbol.