Abstract: A serial digital signal transmission apparatus can transmit HDTV digital serial signals with little jitter while utilizing the SRTS method. In the apparatus, parallel clocks are counted by an N counter to be supplied to the latch circuit, which latches the output count of a p-bit counter, RTSs are supplied from the latch circuit, as the result of comparison gated by a gate circuit is supplied to a PLL circuit and multiplied by N, parallel clocks of 74.25 MHz or 74.25/1.001 MHz, which are inputs to the N counter are regenerated (N is 8, 15 or 16), and transmitted data undergo parallel-to-serial conversion by a PS converter with these parallel clocks.

Abstract: In a rake receiver, a correlation-value calculation section calculates correlation values between spreading codes and reception signals from an input terminal and outputs the calculated correlation values to a delayed-profile creation section and a difference-history creation section. The delayed-profile creation section determines average correlation values and issues the values as a delayed profile to a path selection section. For each reception timing, the difference-history creation section compares the latest correlation value with a previous correlation value held by the difference-history creation section, to determine a difference history, and issues the difference history to the path selection section. The path selection section rearranges the delayed profile in decreasing order of the average correlation values.

Abstract: A digital phase locked loop (DPLL) for providing clock synchronization in backplane bus systems has a loop filter with selectable high and low bandwidth modes. The DPLL is thus capable of respectively attenuating or tracking jitter from an input reference clock.

Abstract: A linear/non-linear adaptive filter for transforming an input signal to an output signal. The present invention also includes a novel GSPT LMS algorithm for significantly reducing complexity. The adaptive filter includes a coefficient updater that can execute a Carry-in operation or a Borrow-in operation to adaptively adjust a filtering coefficient according to whether an updating term signal is a Carry-in signal or a Borrow-in signal.

Abstract: A device for processing an intermediate analogue signal received from a previous system with a baseband processor. The processor includes an ordinary feedback loop for adjusting the strength of the intermediate analogue signal received from the previous system. The processor further includes a first DC offset reduction loop and a second DC offset reduction loop. A programmable filter bank and the corresponding control elements are provided so that the second DC offset reduction loop can reduce the DC offset in a flexible way. In the present invention, the DC offset can be reduced effectively and the gain training period relating to the previous system and the baseband processor can be shortened.