Patents Examined by Julian S Mendel
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Patent number: 12379875Abstract: A method for writing data to a shared write buffer, the method includes (i) receiving, by a processing circuit of a compute node of a storage system, a write request for writing to the shared write buffer an information unit associated with an accessing entity located outside the storage system; wherein the shared write buffer is stored in a non-volatile memory of a storage node of the storage system; the storage node is in communication with the compute node; (ii) determining, by the processing circuit whether to (a) store the information unit in a non-shared segment of the shared write buffer, or (b) store the information unit in a shared segment of the shared write buffer while applying a locking mechanism; wherein the determining is based on parameters, the parameters include a writing parameter of the accessing entity, a writing latency parameter associated with the accessing entity, and a locking timing parameter; and (iii) storing the information unit according to the determination.Type: GrantFiled: December 29, 2023Date of Patent: August 5, 2025Assignee: VAST DATA LTD.Inventors: Hillel Costeff, Asaf Levy
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Patent number: 12299313Abstract: A method is described for proving erasure of a memory. In the method a prover device receives a seed value from a verifier device. The prover device generates a series of data blocks starting with the seed value and a function. The series of data blocks is generated using the function and the seed to generate a first data block of the series of data blocks. Each subsequent data block is generated using the function and a preceding data block until a last data block of the series of data blocks is generated and written to the memory portion. The prover device writes the series of data blocks to the memory to overwrite all memory contents of a memory portion of the prover device. After the data blocks are written to the memory by the prover device, the prover device sends notification of memory erasure to the verifier device.Type: GrantFiled: August 29, 2023Date of Patent: May 13, 2025Assignee: NXP B.V.Inventors: Nikita Veshchikov, Gareth Thomas Davies
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Patent number: 12287976Abstract: Data movement for reducing an environmental load in a hierarchical storage is appropriately determined. A storage system includes an upper-level storage device and a management device. The management device is configured to determine, for each file stored in the upper-level storage device, based on a size of a target file and an access frequency of the target file, and the power consumption information, whether power consumption for holding the target file is to be reduced by moving the target file to the lower-level storage device, and output, when it is determined that the power consumption for holding the target file is to be reduced by moving the target file to the lower-level storage device, an instruction to move the target file from the upper-level storage device to the lower-level storage device.Type: GrantFiled: September 5, 2023Date of Patent: April 29, 2025Assignee: Hitachi Vantara, Ltd.Inventor: Yukiya Maeda
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Patent number: 12271598Abstract: Techniques for transferring data involve: determining a first physical block in a first storage device, the first physical block having a plurality of data blocks stored thereon. The techniques further involve: determining, based on a first data block of the plurality of data blocks, whether a set of logically contiguous data blocks that comprise the first data block exist in the first physical block, the set of data blocks having a target heat greater than a threshold heat. The techniques further involve: transferring, in response to the existence of the set of data blocks in the first physical block, the set of data blocks into a second storage device for contiguous storage in a second physical block of the second storage device. Accordingly, relatively high heat data blocks are transferred to device with higher access speed, thereby reducing data access time, increasing data processing efficiency, and improving user experience.Type: GrantFiled: June 28, 2023Date of Patent: April 8, 2025Assignee: Dell Products L.P.Inventors: Changxu Jiang, Chen Gong, Fei Wang
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Patent number: 12265717Abstract: A memory sub-system, such as a solid-state drive, configured to map a write stream to superblocks without the stream identifying a zone having a predetermined size in a namespace. The memory sub-system is configured to maintain, for the stream, a cursor configured to identify one of the plurality of superblocks as being reserved entirely for the stream; map, based on a superblock identified by the cursor, logical addresses of write commands in a contiguous segment of the stream to physical addresses in the superblock until the superblock is full; store data of write commands in the stream into based on mapping from logical addresses to physical addresses identified via the cursor; and allocate, for the cursor and in response to the superblock identified by the cursor being full, a free superblock available to continue mapping logical addresses to physical address.Type: GrantFiled: June 20, 2023Date of Patent: April 1, 2025Assignee: Micron Technology, Inc.Inventor: Luca Bert
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Patent number: 12265731Abstract: This disclosure provides systems, methods, and devices for memory systems that support partial row refresh operation of a memory system. In a first aspect, a method of refreshing a memory array includes obtaining, by a memory controller from a host device through a channel, partial row refresh information associated with a first row in a memory array and refreshing, by the memory controller, a portion of the first row in the memory array based on the partial row refresh information. Other aspects and features are also claimed and described.Type: GrantFiled: July 13, 2023Date of Patent: April 1, 2025Assignee: QUALCOMM IncorporatedInventors: Subham Panda, Muzaffaruddin Mohammed, Venkatesh Petnikota, Sri Ananda Sai Jannabhatla, Jyothi Ramidi
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Patent number: 12189529Abstract: A Logically Composed System (LCS) data provisioning system includes an orchestrator device that includes a cache subsystem and that is coupled to client devices and storage subsystem(s). When the orchestrator device identifies that a first client device has exclusive access to the storage subsystem(s), it activates read data caching for the storage subsystem(s). The orchestrator device then receives a first read request from the first client device that is directed to first data that is stored in the storage subsystem(s) and, in response, retrieves the first data from the cache subsystem and provides the first data to the first client device. When the orchestrator device identifies that the first client device no longer has exclusive access to the storage subsystem(s), it deactivates the read data caching for the storage subsystem(s).Type: GrantFiled: July 28, 2022Date of Patent: January 7, 2025Assignee: Dell Products L.P.Inventors: Shyamkumar T. Iyer, Xiangping Chen, Xunce Zhou, William Price Dawkins
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Patent number: 12175132Abstract: According to an embodiment, a control device executes control processing based on data stored in a first storage device and a second storage device while performing rewrite in the first storage device. The control device stores a memory image relating to the first storage device at a point of time, at which activation processing is terminated, in a non-limited storage area of the second storage device, the activation processing being based on the data stored in the limited storage area of the second storage device without being based on the data stored in the first storage device. The control device starts the control processing from the point of time, at which the activation processing is terminated, after loading the memory image stored in the non-limited storage area of the second storage device in the first storage device in the activation processing of the control processing.Type: GrantFiled: June 30, 2023Date of Patent: December 24, 2024Assignee: Toshiba Tec Kabushiki KaishaInventor: Yasuhiro Inagaki
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Patent number: 12169650Abstract: A system may include one or more processors configured to receive a frame comprising a quantity of commands, a quantity of storage devices, and a buffer map. In response to the frame, the one or more processors may read, using the buffer map and from a memory, (1) input data for each of one or more storage devices corresponding to the quantity of storage devices and (2) an identifier of each of the one or more storage devices. The one or more processors may send, to the one or more storage devices, a plurality of commands corresponding to the quantity of commands, based at least on the input data for each storage device and the identifier of each storage device.Type: GrantFiled: July 28, 2023Date of Patent: December 17, 2024Assignee: Avago Technologies International Sales Pte. LimitedInventors: Arun Prakash Jana, Amar Deep Kumar
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Patent number: 12164424Abstract: A distributed cache apparatus includes storage comprising a range of stored data and a processing device. A first cache level of the storage is segmented into a plurality of first data sub-ranges of the range of stored data, and each of the first data sub-ranges is associated with one of a first subset of a plurality of node devices. A second cache level of the storage is segmented into a plurality of second data sub-ranges of the range of stored data, and each of the second data sub-ranges is associated with one of a second subset of the node devices. Each of the second data sub-ranges is smaller than each of the first data sub-ranges. The processing device is configured to process a read request for data within the range of stored data by accessing one of the second subset of the node devices.Type: GrantFiled: July 20, 2023Date of Patent: December 10, 2024Assignee: ARKOSE LABS HOLDINGS, INC.Inventors: Du Li, Arnab Mukherji
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Patent number: 12141071Abstract: Provided is a processor that includes a load and store unit (LSU) and a cache memory, and transfers data information from a store queue in the LSU to the cache memory. The cache memory requests an information packet from the LSU when the cache memory determines that an available entry exists in a store queue within the cache memory. The LSU acknowledges the request and transfers an information packet to the cache memory. The LSU anticipates that an additional available entry exists in the cache memory, transmits an additional acknowledgement to the cache memory, and transfers an additional information packet, before receiving an additional request from the cache memory.Type: GrantFiled: July 21, 2022Date of Patent: November 12, 2024Assignee: International Business Machnes CorporationInventors: Shakti Kapoor, Nelson Wu, Manoj Dusanapudi
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Patent number: 12124598Abstract: One or more embodiments of the invention may improve the operation of one or more computing devices in a cluster environment. More specifically, by mapping backups of shared volumes to a cluster client instead of individual data nodes, one or more embodiments of the invention avoid duplicative backups and/or restorations of the same shared assets by the each of the data nodes. Further, if a failure occurs to the particular node the backup may have originated from, in accordance with one or more embodiments of the invention, because the method is agnostic with regards to the individual nodes the backup may have originated from, any remaining data node can discover the backup and perform a restoration or incremental backup. This will provide better protection for the clustered nodes while requiring minimal user/administrator input.Type: GrantFiled: July 25, 2022Date of Patent: October 22, 2024Assignee: Dell Products, L.P.Inventors: Sunil Yadav, Shelesh Chopra, Preeti Varma
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Patent number: 12124731Abstract: A technique is directed to processing metadata changes. The technique involves designating a first tablet to ingest metadata changes and a second tablet to destage previously ingested metadata changes, the first tablet being partitioned into a first reserved space and a first regular space that form a first memory pool, and the second tablet being partitioned into a second reserved space and a second regular space that form a second memory pool. The technique further involves, while the first tablet is designated to ingest metadata changes and the second tablet is designated to destage previously ingested metadata changes, ingesting metadata changes into the first tablet and destaging the previously ingested metadata changes from the second tablet. The technique further involves, when the first tablet becomes full, performing a switch operation that designates the second tablet to ingest metadata changes and the first tablet to destage previously ingested metadata changes.Type: GrantFiled: July 25, 2022Date of Patent: October 22, 2024Assignee: Dell Products L.P.Inventors: Bar David, Vladimir Shveidel