Abstract: In a ball grid array (BGA) package, a first stiffener is attached to a surface of a substrate. A second stiffener is attached to the surface of the substrate to be co-planar with the first stiffener. The second stiffener is separated from the first stiffener by a channel therebetween. An integrated circuit (IC) die is mounted to a surface of the second stiffener.

Abstract: Semiconductor equipment includes: a first lead frame having a first semiconductor device; a second lead frame having a second semiconductor device; a thermal resistor for preventing heat transfer from the first lead frame to the second lead frame; and a temperature sensitive device for detecting operational temperature of the first semiconductor device. The first lead frame is separated from the second lead frame by a predetermined distance. The thermal resistor is disposed in a clearance between the first lead frame and the second lead frame. The second semiconductor device controls to restrict operation of the first semiconductor device when the operational temperature of the first semiconductor device is higher than a predetermined temperature.

Abstract: An improved electromagnetic shielding structure has been discovered. In one embodiment of the invention, an apparatus includes an inductor and an electrically conductive enclosure that electromagnetically shields the inductor. The electrically conductive enclosure has an aperture at least as large as the inductor. The aperture is substantially centered around a projected surface of the inductor. The apparatus may include one or more electrically conductive links extending across the aperture and electrically coupled to the electrically conductive enclosure. The electrically conductive links reduce an effect of electromagnetic signals external to the electrically conductive enclosure on the inductor.

Abstract: An electronic device may include first, second, and third substrates wherein the second electronic substrate is between the first and second electronic substrates. A first electrical and mechanical connection may be provided between the first and third electronic substrates, and a second electrical and mechanical connection may be provided between the second and third electronic substrates. In addition or in an alternative, an electronic device may include a printed circuit board, a first electronic substrate on the printed circuit board, a second electronic substrate on the first electronic substrate, and a third electronic substrate on the second electronic substrate. More particularly, the first electronic substrate may be between the printed circuit board and the second electronic substrate, and the second electronic substrate may be between the first and third electronic substrates.

Abstract: Apparatus and system, as well as fabrication methods therefor, may include a thermal intermediate structure comprised of a plurality of carbon nanotubes some of which have organic moieties attached thereto to tether the nanotubes to at least one of a die and a heat sink. The organic moieties include thiol linkers and amide linkers.

Abstract: A semiconductor device includes a first surface faced to a mounting board when the semiconductor device is placed over the mounting board and a second surface opposed to the first surface. The semiconductor device also includes a position reference portion which is provided in an area including sides of the second surface and which has an optical reflection factor different from that of the mounting board.

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.

Abstract: In a multilayer printed wiring board having a plurality of laminated resin layers, a plurality of wiring patterns formed on the interfacial surface of the resin layers, and a plurality of lands formed on the outermost layer of the resin layers and on which the solder is provided, at least one of the wiring patterns has a plurality of openings in the form of a mesh, the size of openings of the wiring patterns in a region corresponding to the position of solder in which a stress generated in the solder provided on the lands becomes a value larger than a desired value due to thermal deformation of the semiconductor device and the multilayer printed wiring board is larger than that of openings in the other regions.

Abstract: A semiconductor package assembly is presented. The assembly comprises a first chip and a second chip. The back surfaces of the first and the second chips are thermally attached through a die attach material. The front surface of the first chip is attached to a substrate through bumps. A heat spreader extends from a surface of the semiconductor package assembly into the semiconductor package assembly and thermally attaches to the back surface of the first chip or the front surface of the second chip. Depending on the sizes of the chips and the location of the bonding pads, the heat spreader may be attached to the back surface of the first chip or the front surface of the second chip.

Abstract: Arrangements are used for minimizing signal path discontinuities.

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract: An electronic component includes a semiconductor chip with an active front face and a passive rear face, with contact connections and contact surfaces respectively being provided on the active front face and/or on the passive rear face, and with conductive connections being provided in the form of structured conductive tracks for providing an electrical connection from the active front face to the passive rear face. An electronic assembly formed of stacked semiconductor chips, and a method for producing the electronic component and the electronic assembly are also provided.

Abstract: A package substrate for carrying a chip with a plurality of bumps thereon is provided. The package substrate includes a first substrate, and an interposer. The first substrate has a first circuit layer disposed on a surface thereof. The interposer includes a second substrate and a second circuit layer formed thereon. The second circuit layer comprises a plurality of bonding pads and traces. The traces are electrically connected to the corresponding bonding pads. Furthermore, the bonding pads are used for being connected to the bumps. The second circuit layer of the interposer is physically and electrically connected to the first circuit layer of the first substrate, and the second substrate and the first substrate are made of different materials.

Abstract: A method and apparatus for improving the latchup tolerance of circuits embedded in an integrated circuit while avoiding the introduction of noise from such tolerance into the power rails.

Abstract: One embodiment of a micro-electronic device includes a substrate including micro-electronic components thereon, and a cover including a ring of sealing material secured to the substrate and a raised ring of material positioned opposite the cover from the ring of sealing material.

Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

Abstract: A circuit board comprises a dielectric layer, a net of first power supply lines for providing a first reference voltage plane and a net of second power supply lines for providing a second reference voltage plane. The nets of first and second power supply lines are arranged such that first power supply lines and second power supply lines are alternately arranged in the direction of a first surface of the dielectric layer.