Abstract: A vertically oriented FET having a self-aligned dog-bone structure as well as a method for fabricating the same are provided. Specifically, the vertically oriented FET includes a channel region, a source region and a drain region. The channel region has a first horizontal width and the source and drain regions having a second horizontal width that is greater than the first horizontal width. Each of the source and drain regions have tapered portions abutting the channel region with a horizontal width that varies in a substantially linear manner from the first horizontal width to the second horizontal width.

Abstract: An inductive structure integrated in a semiconductor substrate, comprising at least a conductive element insulated from the substrate, comprising an insulating structure, which is formed inside said semiconductor substrate and built close to said conductor element, so that the resistance of said substrate is increased and the parasitic currents induced by the conductor element in the substrate are decreased. The insulating structure including a plurality of insulating elements each surrounding a respective one of a plurality of semiconductor islands of the substrate.

Abstract: By depositing a diffusion prevention film 7 constructed of an oxide of aluminum containing barium and heat-treating the diffusion prevention film 7 in the atmosphere of a mixed gas of oxygen and carbon dioxide, carbon dioxide is made to adsorb to the barium contained in the diffusion prevention film 7. The diffusion prevention film can effectively restrain the permeation of hydrogen and has an excellent hydrogen barrier property. By using the diffusion prevention film for a capacitor, a high-yield semiconductor storage device having the capacitor of a stable ferroelectric characteristic or high dielectric characteristic can be obtained.

Abstract: A semiconductor component includes a semiconductor substrate (110) having first and second portions (111, 112) with a first conductivity type, a transistor (120) at least partially located in the semiconductor substrate, and a switching circuit (150, 350, 650, 850). The transistor includes (i) a first doped region in the first portion of the semiconductor substrate and having the first conductivity type (ii) a terminal, which includes a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region, and (iii) a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate. The switching circuit is electrically coupled to the third doped region to adjust the bias of the third doped region.

Abstract: An integrated circuit chip is provided having both a conventional DRAM vertical transfer device and an integrated vertical storage capacitor or anti-fuse that can be accessed directly without having to turn on a transfer gate. The mechanism for accessing the integrated capacitor or anti-fuse directly can be a modified doping profile within the vertical cell that provides a low resistance punch-through FET. Alternatively, the mechanism can be a pair of overlapping or nearly overlapping diffusions within the vertical cell.

Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5 to 6 um wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

Abstract: It is intended to provide a semiconductor device in which a fuse required conventionally is omitted and an initial resistance value can be maintained even under stress imposed due to packaging or the like, a high-accuracy bleeder resistance circuit that can maintain an accurate voltage division ratio, and a high-accuracy semiconductor device with such a bleeder resistance circuit, for example, a voltage detector or a voltage regulator. In a semiconductor device with a resistor, the resistor includes a P-type resistor made of a P-type semiconductor and an N-type resistor made of an N-type semiconductor which are combined to form one body, and the P-type resistor and the N-type resistor are placed on low and high potential sides, respectively. The P-N junction is irradiated with a laser beam or the like, whereby rectification is damaged to allow conduction.

Abstract: A semiconductor device (20) includes an isolated p-well (22) formed in a substrate (21) by a buried n-well (25) and an n-well ring (24). The n-well ring (24) extends from a surface of the semiconductor device (20) to the buried n-well (25). The isolated p-well (22) includes a plurality of n-well plugs (27) extending from the surface of the semiconductor device (20) into the isolated p-well (22) and contacting the buried n-well (25). The plurality of n-well plugs (27) reduces an n-well resistance to provide better noise isolation for high frequency signals.

Abstract: A semiconductor device comprises: a first resistor which has a plurality of first connection points to be selectively connected to an input terminal of an amplifier and has both ends to which a voltage is applied; and a second resistor which has one end to be connected to an output terminal of the amplifier and has a plurality of second connection points to be selectively connected to a feedback input terminal of the amplifier. One of the first connection points and one of the second connection points are selected in such a manner that a voltage at the output terminal of the amplifier becomes constant. Each of the first and second resistors is formed of first reference resistors having a first reference length and second reference resistors having a second reference length as many as needed, both of which are connected by an interconnect layer. The first and second reference resistors for forming the first and second resistors are provided in an effective resistor region and are regularly arranged.

Abstract: The invention relates to a semiconductor component with a base zone (3) extending in a lateral direction (x) of a first type of conductivity (n) and at least two contact areas (1, 2) for connection to electric contacts (A, K) which zones are separate at least from the base zone (3) in the lateral direction (x). A base material of the base zone (3) is silicon (Si) and has a dopant concentration of 1012 to 5×1014 cm−3 and a respective dopant concentration (NA) along a lateral direction (x) of less than 2×1012 cm−2 determined by integrating the dopant concentration across the vertical thickness of the base area (3). The semiconductor component further comprises compensation layers (6, 6a, 6b, 6c, 7, 7a, 7b, 7c, 8) of a second type of conductivity (p) opposed to the first type of conductivity. Said layers extend inside or outside the base area in a lateral direction (x).