Abstract: A hard disk controller having a latency-independent interface comprises a data gate circuit that transmits a data gate signal. A data circuit transmits or receives data under control of the data gate signal. A media gate circuit transmits a media gate signal. A mode selection circuit transmits mode selection information under control of the media gate signal, wherein said data gate signal controls the transfer of data between the hard disk controller and a read/write channel in accordance with the media gate signal.

Abstract: To provide a status display apparatus or the like which can permit the user of a plurality of nodes connected by a serial bus according to the serial bus standard to recognize whether the transmission of the audio information or the like has become possible by the connection between the nodes. A status display apparatus included in a receiver R for transmitting/receiving audio information with a player to display the status of the receiver comprises a system control unit 13 and an indicator 15B which makes inquiry about whether the player P has a configuration for transmitting/receiving the audio information to/from the receiver R and upon confirmation that the player P has the required configuration, displays that the player P has such a configuration.

Abstract: Systems, methods, apparatus and software can implement a multipathing driver using dynamically loadable device policy modules that provide device specific functionality for providing at least one of input/output (I/O) operation scheduling, path selection, and I/O operation error analysis. Because the device policy modules include device specific functionality, various different devices from different manufacturers can be more efficiently and robustly supported.

Abstract: A method and system for accessing devices through use of an abstraction layer interface that “hides” the access methods from components accessing the devices, such as device drivers and OPROMs. The abstraction layer interface includes a set of resource access methods and a database containing bus, device, function and resource information for various devices in a system. During an initialization process, bus and device configuration information is determined and stored in the database. When an application or operating system requests access to a device, the application or OS uses the device's device driver or OPROM to pass identification information, resource information and one or more resource access commands to the abstraction layer interface, which then verifies the identification information against the database, and converts the resource access request into appropriate resource access methods that are used to access the device.

Abstract: A method for generating an interrupt signal for a media access controller (MAC) in communication with a computer host and an external network is disclosed. The method includes steps of asserting an interrupt signal to the computer host when at least one data packet is to be transferred from a memory, performing a corresponding interrupt service of the computer host in response to the interrupt signal for freeing a memory space occupied by the data packet being transferred from the memory, and deasserting the interrupt signal until the corresponding interrupt service is finished and a predetermined delay period is up. In addition, a media access controller (MAC) is also disclosed. The MAC includes a timer for counting a predetermined delay period after the interrupt service has been finished.

Abstract: A switching transistor is placed between a serial port of a RS232 device and a parallel port of a TTL microcontroller. Selective activation of the switching transistor permits a high voltage signal to be transmitted from the power supply rail of the TTL microcontroller to the RXD pin of the RS232 device, where the signal is interpreted as a logical low. This step takes advantage of the fact that the RS232 standard interprets any voltage received at the RXD pin greater than a receiver threshold value to be a logical low. Selective deactivation of the switching transistor isolates the RS232 port from the non-RS232 device, permitting negative voltage signal output by the TXD pin of the idling RS232 port to be conveyed back to the RS232 port at the RXD pin. This negative voltage signal is interpreted by the RS232 port as a logical high signal.

Abstract: Once attached to a slot of a personal digital assistant, a card module executes an application-specific program and transmits a result obtained thereby to the personal digital assistant. The thus received execution result is outputted from an output part. Accordingly, the output part can be provided for shared use among several card modules for output of the execution result.

Abstract: Embodiments of the present invention relate to an apparatus including a first processor module, a second processor module, and a bus. The bus is coupled to the first processor module and the second processor module. The bus is configured to transmit both processor related communication and memory related communication. In embodiments, the first processor module includes a first central processing unit and the second processing module includes a second central processing unit. Accordingly, in embodiments of the present invention, a single bus can be used to communicate between processors and memories. The present invention is useful for real time duplication of memory, high speed duplication of memory, and/or a coherency check of memory between a first processing module and a second processing module.

Abstract: A loop of delayed read commands is established from a larger set of queued commands. Upon recognizing a delay in completing a first read command which is followed by a second read command, the loop is established by setting loop start pointer to identify the first delayed read command and setting a loop end pointer to identify the second read command. Upon recognizing a delay in completing the second read command which is followed by a third read command, the loop end pointer is advanced to identify the third read command. All of the read commands in the loop at and between the loop start pointer and the loop end pointer are completed before attempting to complete other commands in the queue not within the loop.

Abstract: The utilization of various individual components of a channel is determined in order to learn which portion of a channel is busy and to what extent that portion is busy. The determination of a component's utilization is dependent on the type of component, as well as the operational characteristics of that component.

Abstract: It is the object of the invention to optimise the allocation of address ranges to modules of an integrated circuit. Since according to the invention the address ranges in the address space are selectable through a central address management, the usage of the address space capacity can be optimised according to the current load factor. Flexible usage of the address space is enabled by choosing the position of the address range to be selected and the size of the address range. The address range can be assigned automatically by a software program. The software program is for example designed in such a way that it executes a fair distribution of the address ranges to the existing modules or those modules that currently need an address range. Provided there are no overlaps with other address ranges, the address ranges to be assigned can be chosen as wished. User-specific programming can be used to allocate specific address ranges to individual modules.

Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

Abstract: A method for dynamic preemption of read returns over a half-duplex bus during heavy loading conditions involves asserting a preempt signal by a first agent to indicate that the first agent has a read request pending for transmission over the half-duplex bus. A second agent then samples the preempt signal sent by the first agent. The second agent relinquishes ownership of the half-duplex bus responsive to the preempt signal to allow the read request to be sent across the half-duplex bus.

Abstract: An input circuit is coupled to a first bus to transfer a delayed transaction (DT) data having a transaction identifier to one of N buffers. The input circuit is dynamically configured according to a bus frequency. N is a positive integer. The one of the N buffers is associated with the transaction identifier. An output circuit is coupled to the buffers to transfer the DT data from the one of the N buffers to a second bus operating at the bus frequency. The output circuit is dynamically configured according to the bus frequency.

Abstract: A storage processor particularly suited to RAID systems provides high throughput for applications such as streaming video data. An embodiment is configured as an ASIC with a high degree of parallelism in its interconnections. The preferred embodiment provides a store and forward architecture configured around a switch with prioritization on data pathways critical to high throughput.

Abstract: A computer system with a bus arbitration system adaptively assigns priority to devices on the bus based upon workload. A bus arbiter receives request signals from bus devices that require bus access, and also receives a signal indicating the pending workload of that device, as measured by the number of operations pending in a queue in that device. Based on the workload signal, the bus arbiter breaks any arbitration conflicts by assigning priority to the device with the greatest workload. In the event of ties, the bus arbiter may use other arbitration schemes to break ties between devices with equal workloads.

Abstract: Once attached to a slot of a personal digital assistant PDA, a card module CM executes an application-specific program and transmits a result obtained thereby to the personal digital assistant PDA. The thus received execution result is outputted from an output part. Accordingly, the output part can be provided for shared use among several card modules CM for output of the execution result.

Abstract: A processing system comprises: a shared system resource; a plurality of control devices, each assignable with a task having a predetermined maximum time to complete, the control devices time sharing the system resource in the process of performing their assigned tasks in accordance with a predetermined sequence; and an arbiter circuit for regulating access of said control devices to the system resource. Each control device includes a throttle circuit coupled to the arbiter circuit and individually programmable to control in cooperation with the arbiter circuit utilization of the system resource by the corresponding control device so that each control device may perform its task within the predetermined maximum completion time thereof.

Abstract: A computer system comprising mass storage, a system bus connected to the mass storage, and a processor unit connected to the system bus. A library of standard functions is stored in the mass storage. Each library function is stored in at least one of two versions. The first version is obtained from compilation of firmware code, as is conventional. The second version is obtained from compilation of firmware code and comprises a set of configuration data for loading into a field programmable gate array (FPGA). The computer system is provided with a FPGA connected to the system bus which can be configured by the second versions of the library functions so that these can be performed in the FPGA, instead of in the processor. The apparatus and method are well suited to libraries of database search engine functions. Performance advantages can be obtained by executing function calls in the FPGA.

Abstract: A system and method for synchronizing devices which can couple to the Internet, or any network. The system includes a first sync engine on the first system interfacing with data on the first system to provide difference information. A data store is coupled to the network and in communication with the first and second systems. A second sync engine is provided on the second system coupled to receive the difference information from the data store via the network, and interface with data on the second system to update said data on the second system with said difference information. Difference information is transmitted to the data store by the first sync engine and received from the data store from the second sync engine.