Patents Examined by K Christianson
  • Patent number: 6342405
    Abstract: Methods are disclosed for forming Group III-arsenide-nitride semiconductor materials. Group III elements are combined with group V elements, including at least nitrogen and arsenic, in concentrations chosen to lattice match commercially available crystalline substrates. Epitaxial growth of these III-V crystals results in direct bandgap materials, which can be used in applications such as light emitting diodes and lasers. Varying the concentrations of the elements in the III-V crystals varies the bandgaps, such that materials emitting light spanning the visible spectra, as well as mid-IR and near-UV emitters, can be created. Conversely, such material can be used to create devices that acquire light and convert the light to electricity, for applications such as full color photodetectors and solar energy collectors. The growth of the III-V crystals can be accomplished by growing thin layers of elements or compounds in sequences that result in the overall lattice match and bandgap desired.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: January 29, 2002
    Assignee: JDS Uniphase Corporation
    Inventors: Jo S. Major, David F. Welch, Donald R. Scifres
  • Patent number: 6326280
    Abstract: The present invention provides new and improved thin film semiconductors and methods for making crystalline semiconductor thin films which may be bonded to different kinds of substrates. The thin films may be flexible. In accordance with preferred methods, a multi-layer porous structure including two or more porous layers having different porosities is formed in a semiconductor substrate. A semiconductor thin film is grown on the porous structure. Electrodes and/or a desired support substrate may be attached to the grown film. The grown film is separated from the semiconductor substrate along a line of weakness defined in the porous structure. The separated thin film attached to the support substrate may be further processed to provide improved film products, solar panels and light emitting diode devices. These thin film semiconductors are excellent in crystallinity and may be inexpensively produced, thereby enabling production of solar cells and light emitting diodes at lower cost.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: December 4, 2001
    Assignee: Sony Corporation
    Inventor: Hiroshi Tayanaka
  • Patent number: 6323053
    Abstract: As a pretreatment of a substrate, a substrate of Si having the (111) surface orientation as a main surface is soaked in hydrofluoric acid, so as to form a H atomic layer for terminating dangling bonds on the main surface of the substrate. Then, the substrate is placed in a highly evacuated growth chamber in an MBE system, and a Ga molecular beam and a Se molecular beam are supplied onto the H atomic layer on the substrate, so as to grow a buffer layer of GaSe, that is, a van der Waals crystal. Next, with the supply of the Se molecular beam stopped, a N2 gas activated by using radio frequency or electron cyclotron resonance is supplied instead as a nitrogen source onto the buffer layer on the substrate, so as to form a semiconductor layer of GaN.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: November 27, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Nishikawa, Yoichi Sasai, Makoto Kitabatake
  • Patent number: 6312970
    Abstract: In a CCD type solid state image pickup device including a semiconductor substrate having photo/electro conversion portions and a first insulating layer formed on the semiconductor substrate, a plurality of charge transfer electrodes are formed on the first insulating layer and are a double structure formed by a first conductive layer and a second conductive layer having a lower resistance value than the first conductive layer. A second insulating layer is interposed between two adjacent ones of the charge transfer electrodes.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: November 6, 2001
    Assignee: NEC Corporation
    Inventor: Chihiro Ogawa
  • Patent number: 6297068
    Abstract: The present invention provides a method for making highly compact vertical cavity surface emitting laser by a lateral oxidation process. Specifically, the present invention allows for the use of well-controlled oxidized regions to bound and to define the aperture of a laser structure in a current controlling oxidation layer, wherein the aperture comprises a conductive region in the oxidation layer. These oxidized regions are formed by the use of a pre-defined bordering pattern of cavities etched in the laser structure, which allow the embedded oxidation layer to be oxidized, and which results in a highly reproducible and manufacturable process.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: October 2, 2001
    Assignee: Xerox Corporation
    Inventor: Robert L. Thornton
  • Patent number: 6204087
    Abstract: A radiation-damage resistant radiation detector with preferably three dimensional collection electrodes may be formed on a substrate that is a semiconductor or an insulator, and may be operated in avalanche mode to increase detection output. A detector comprising interleaved n-type and p-type preferably three dimensional electrodes formed in an area whose perimeter is an active trench. The trench is doped with dopant of opposite type polarity to that of the nearest electrodes, with respect to which the trench is reverse biased. The trench itself can act as a detector element, and the overall device exhibits edge-to-edge active detection. A plurality of such detectors may be arrayed in a plane to provide an essentially seamless large area detector suitable for medical and research applications, including synchrotron studies.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: March 20, 2001
    Assignee: University of Hawai'i
    Inventors: Sherwood Parker, Christopher J. Kenney
  • Patent number: 6159762
    Abstract: Method for manufacturing an absolute pressure sensor as micromechanical component on a silicon substrate, whereby a cavity (4) is etched out in an auxiliary layer (3) under a membrane layer (5) through etching openings (6), the etching openings are closed with a passivation layer (7), whereby a specific etching opening (11) is re-opened in a via hole etching and this opening is re-closed with a metallization or dielectric material (10, 12) in a following process step that ensues at low pressure.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: December 12, 2000
    Inventors: Thomas Scheiter, Christofer Hierold, Ulrich Naher
  • Patent number: 6103600
    Abstract: A quantum dot and quantum fine wire forming method is provided which can allow control of the position for crystalline particle growth and enables formation of particles with high uniformity in size and density and with high reproducibility. After an Si substrate is formed with a step by a dry etching method, an SiO.sub.2 film is formed on the surface of the substrate. The interior of a reaction chamber is evacuated to a vacuum of 10.sup.-8 Torr, and then an Si.sub.2 H.sub.6 gas is introduced into the reaction chamber to flow therein so that Si crystal particles (quantum dots) are formed along the step. The step is formed by conventional photolithography and dry etching; therefore, the position for quantum dot growth can be easily controlled. By controlling the rate and time period of gas flow and the temperature of the substrate it is possible to form quantum fine wires, and to control the size of quantum dots and/or thickness of quantum fine wires.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: August 15, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Yasumori Fukushima, Kenta Nakamura
  • Patent number: 6060338
    Abstract: A method of fabricating a field effect transistor including forming a gate electrode on an electrically insulating substrate; forming an electrically insulating film on the substrate covering the gate electrode; forming source and drain electrodes on the electrically insulating film on opposite sides of the gate electrode; forming a semiconducting film of a .pi.-conjugated polymer on the source and drain electrodes and on the electrically insulating film between the source and drain electrodes.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: May 9, 2000
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Sumitomo Chemical Company, Limited
    Inventors: Toshihiko Tanaka, Syuji Doi, Hiroshi Koezuka, Akira Tsumura, Hiroyuki Fuchigami
  • Patent number: 6030887
    Abstract: Process for the preparation of an epitaxial wafer having a total thickness variation and/or site total indicated reading of less than about 1.0 .mu.ms. The distance between the front and back surfaces of the epitaxial wafer at discrete positions on the front surface is measured to generate thickness profile data. Additional stock is removed from the front surface of the epitaxial wafer in a stock removal step to reduce the thickness of the epitaxial wafer to the target thickness, T.sub.t, with the amount of stock being removed at each of said discrete positions being determined after taking into account the thickness profile data and T.sub.t.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: February 29, 2000
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Ankur H. Desai, David L. Vadnais, Robert W. Standley
  • Patent number: 6030849
    Abstract: On an entire surface of a substrate of sapphire having a projection with a width in the lateral direction of approximately 10 .mu.m thereon, a first semiconductor layer of Al.sub.y Ga.sub.1-y N and a second semiconductor layer of In.sub.x Ga.sub.1-x N are successively grown by MOVPE. In this manner, an island-like stacked substance including the isolated first semiconductor layer and the isolated second semiconductor layer can be formed on the top surface of the projection of the substrate.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: February 29, 2000
    Assignee: Matsushita Electric Industrial Co. Ltd.
    Inventors: Yoshiaki Hasegawa, Akihiko Ishibashi, Nobuyuki Uemura, Yuzaburo Ban, Masahiro Kume, Yoshihiro Hara, Isao Kidoguchi, Ayumu Tsujimura
  • Patent number: 6013563
    Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: January 11, 2000
    Assignee: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Nathan W. Cheung
  • Patent number: 6001665
    Abstract: The present invention provides a method for producing a semiconductor laser device having at least a light emitting section, a cap layer and an electrode successively formed on a semiconductor substrate, the light emitting section including a light emitting layer located approximately in a middle of a thickness of the device. The method includes the step of growing the light emitting section and the cap layer using a vapor phase epitaxy method, wherein a growth rate of the cap layer is greater than a growth rate of the light emitting section.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: December 14, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takashi Ishizumi, Shinji Kaneiwa
  • Patent number: 5998298
    Abstract: A method is disclosed for fabricating a two- or three-dimensional photonic bandgap structure (also termed a photonic crystal, photonic lattice, or photonic dielectric structure). The method uses microelectronic integrated circuit (IC) processes to fabricate the photonic bandgap structure directly upon a silicon substrate. One or more layers of arrayed elements used to form the structure are deposited and patterned, with chemical-mechanical polishing being used to planarize each layer for uniformity and a precise vertical tolerancing of the layer. The use of chemical-mechanical planarization allows the photonic bandgap structure to be formed over a large area with a layer uniformity of about two-percent. Air-gap photonic bandgap structures can also be formed by removing a spacer material separating the arrayed elements by selective etching. The method is useful for fabricating photonic bandgap structures including Fabry-Perot resonators and optical filters for use at wavelengths in the range of about 0.2-20 .
    Type: Grant
    Filed: April 28, 1998
    Date of Patent: December 7, 1999
    Assignee: Sandia Corporation
    Inventors: James G. Fleming, Shawn-Yu Lin, Dale L. Hetherington, Bradley K. Smith
  • Patent number: 5985685
    Abstract: A semiconductor optical device, for example a laser, has a composite optical waveguide including a tapered, MQW active waveguide in optical contact with a substantially planar, passive waveguide. The fundamental optical mode supported by the composite waveguide varies along the length of the composite waveguide so that, in a laser, the laser mode is enlarged and is a better match to single mode optical fibre. A method for making such semiconductor optical devices is also disclosed.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: November 16, 1999
    Assignee: British Telecommunications public limited company
    Inventors: Ian F. Lealman, Michael J. Robertson, Simon D. Perrin
  • Patent number: 5940723
    Abstract: The specification describes a process for growing device quality III-V heteroepitaxial layers without the use of buffer layers, i.e. largely defect free layers with thicknesses greater than 50 Angstroms directly on the III-V substrate. These high quality heteroepitaxial layers are grown by low temperature MBE.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: August 17, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: John Edward Cunningham, Keith Wayne Goossen
  • Patent number: 5920766
    Abstract: A red laser structure has an inverted or p-side down orientation. The red laser structure is inverted and wafer fused to a blue laser structure to form a red/blue monolithic integrated laser structure. The top semiconductor layer of the inverted red laser structure is a GaInP fusion bonding layer which will be wafer fused to the top semiconductor layer of the blue laser structure which is a GaN cladding/contact layer.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: July 6, 1999
    Assignee: Xerox Corporation
    Inventor: Philip D. Floyd
  • Patent number: 5891746
    Abstract: The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the device's performance characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: April 6, 1999
    Assignee: International Business Machines Corporation
    Inventor: Daniel M. Kuchta