Patents Examined by K. Cuneo
-
Patent number: 7161874Abstract: The power generated by a power generating means (1) of a power-generating type electronic clock is measured by a first power generating sensing means (101) and a second power generating sensing means (102). The power generation level required when the operation is changed from a normal mode to a power-saving mode and the power generation level required when the operation is changed from the power-saving mode back to the normal mode are made different to prevent the phenomenon that the operation changes frequently by imparting hysteresis characteristics to the power generation level which causes a change in the mode, thereby improving the power-saving effect.Type: GrantFiled: June 21, 2001Date of Patent: January 9, 2007Assignee: Citizen Watch Co., Ltd.Inventors: Masakazu Ichikawa, Isao Kitazawa
-
Patent number: 7136288Abstract: A memory device is provided with a memory chip and a controller, which can be connected to a computer via a USB connector. The memory device is implemented in the form of a flat memory card, wherein the USB connector is movable between a position of rest, in which the connector is accommodated in an opening of the memory card, and an operative position, in which the connector projects beyond the perimeter of the memory card. The opening is a rectangular opening lying entirely within the perimeter of the memory card, wherein in the position of rest the USB connector is positioned entirely within the confines of the memory card.Type: GrantFiled: December 23, 2003Date of Patent: November 14, 2006Assignee: Freecom Technologies B.V.Inventor: Dirk Cornelis Hoogerdijk
-
Patent number: 7133296Abstract: A portable USB storage device includes a case, a USB port, and a control device. The case contains therein a data storage. The USB port can be inputted into the case in a sliding motion. The control device selectively controls a location of the USB port to keep the USB port.Type: GrantFiled: November 5, 2003Date of Patent: November 7, 2006Assignee: Electronics and Telecommunications Research InstituteInventors: Dae Seon Choi, Hee Sun Kim, Taesung Kim, Jong-Hyuk Roh, Sang Rae Cho, Young Seob Cho, Seung Hun Jin
-
Patent number: 7095627Abstract: A shield structure that transmits a radio wave in a specific frequency band and that exhibits a high shield characteristic in other bands. An opening portion having a specific shape and a specific perimeter length is formed on a conductor. A filter having a specific shape and a specific size is connected to the opening portion.Type: GrantFiled: January 14, 2004Date of Patent: August 22, 2006Assignee: Hitachi, Ltd.Inventor: Hitoshi Yokota
-
Patent number: 7088593Abstract: The present invention provides a shield case comprising a frame body having an interior divided by partition plates and housing electronic components therein and a closure for providing electric shield by covering an opening portion of the frame body, and having a slit piece integrally formed with the closure by cutting out a part of the closure along a periphery except for a base portion to a raised form, the slit piece for coming into contact with an end of the partition plate, the slit piece being formed in a gutter shape from the base portion to the other end. Furthermore, the slit piece has the gutter shape which becomes greater in curvature radius from the base portion to the other end. This enables the shield case of the high-frequency device of the present invention to strengthen the contact between the slit piece formed with the closure for providing grounding and the partition plates provided within the frame body, whereby the reliable high-frequency device can be provided.Type: GrantFiled: March 27, 2002Date of Patent: August 8, 2006Assignees: Sanyo Electric Co., Ltd., Sanyo Tuner Industries Co., Ltd.Inventor: Akira Aochi
-
Patent number: 7084353Abstract: A circuit board has a layer of non-conductive material, and a set of soldering pads disposed on the layer of non-conductive material. The set of soldering pads defines a common axis that extends substantially through a midline of each soldering pad. Each soldering pad has, as measured perpendicularly through the common axis, an inner width, a first edge width and a second edge width. The inner width is longer than each of the first and second edge widths. Additionally, the first edge width is longer than the second edge width. Accordingly, the pads have less corner spaces that could otherwise, with melted solder, draw a circuit board component into an incorrect orientation which would result in incorrect mounting of the component. As a result, the component terminals tend to be drawn toward central regions of each pad for robust and reliable solder joint formation.Type: GrantFiled: December 11, 2002Date of Patent: August 1, 2006Assignee: EMC CorporationInventor: Stuart D. Downes
-
Patent number: 7061772Abstract: In an electronic circuit having an integrated circuit (110) having a power supply terminal, a noise filter disposed adjacent to the integrated circuit, and a printed board (101) having a pattern for supplying a power supply to the power supply terminals of the integrated circuit through the noise filter, the noise filter consists of a transmission line type noise filter (121–124) for removing noises having a wide frequency band.Type: GrantFiled: July 29, 2003Date of Patent: June 13, 2006Assignee: NEC TOKIN CorporationInventors: Satoshi Arai, Takayuki Inoi, Yoshihiko Saiki, Sadamu Toita
-
Patent number: 7022919Abstract: An I/O routing pattern method is disclosed, for use with heterogeneous printed circuit boards (PCBs), such as those embedded with a reinforcement material, for example, a fiberglass weave. Traces are routed on the PCB so as to reduce sensitivity to changes in the dielectric constant (Dk), which are brought about by the strands of reinforcement material contained within the PCB laminate. The method minimizes the local variations, such as the Dk, time of flight, and capacitance variations, that are observed with traditional routing methods on heterogeneous PCBs.Type: GrantFiled: June 30, 2003Date of Patent: April 4, 2006Assignee: Intel CorporationInventors: Gary A. Brist, Gary B. Long, William O. Alger, Dennis J. Miller
-
Patent number: 7012197Abstract: A multi-layer printed circuit board includes an insulation substrate; a surface conductive pattern disposed on a surface of the insulation substrate; and an inner conductive pattern embedded in the insulation substrate. The surface conductive pattern has a surface roughness on an insulation substrate side, the surface roughness of the surface conductive pattern being larger than that of the inner conductive pattern.Type: GrantFiled: April 1, 2004Date of Patent: March 14, 2006Assignee: Denso CorporationInventors: Toshikazu Harada, Koji Kondo
-
Patent number: 6900988Abstract: A connecting device with a low height comprises a connector part, and a set of metal terminals. The connector part has a height compatible with the height of an inner space in a standard USB interface slot socket so as to be inserted into the standard USB interface slot socket. The set of metal terminals is arranged on the connector part and composed of a plurality of metal sheets and each metal sheet has an end disposed in the connector part and another end extending outward the connector part. The first end of the respective metal sheet in the set of metal terminals contacts with internal electronic signal of the standard USB interface slot socket and the second end of the respective metal sheet is soldered to a printed circuit board. Furthermore, the low height connecting device can be revised as an electronic connecting device capable of being inserted into the USB slot socket so that both of the connecting devices can be used in a dual interface memory storage apparatus or a memory storage apparatus.Type: GrantFiled: August 11, 2003Date of Patent: May 31, 2005Assignee: Power Quotient International Ltd.Inventor: Sheng Shun Yen
-
Patent number: 6891110Abstract: A radio frequency identification tag comprising a first substrate and a second substrate is disclosed. An antenna element is disposed on the first substrate, and a first contact pad and a second contact pad is disposed on the second substrate. A circuit is coupled to the first and second contact pads, and the first and second contact pads are designed to make electrical contact with the antenna element.Type: GrantFiled: March 21, 2000Date of Patent: May 10, 2005Assignee: Motorola, Inc.Inventors: Thomas J. Pennaz, Noel H. Eberhardt
-
Patent number: 6838767Abstract: Provided is a technique which permits production of a semiconductor device having, integrated therein, a semiconductor chip smaller in external size than an ordinary semiconductor chip without lowering the production yield. The semiconductor device according to the present invention comprises a substrate having a square-shaped plane and having an interconnection formed on a first surface (chip mounting surface) of first and second opposite surfaces; a semiconductor chip which is mounted on the first surface of said substrate and has an electrode formed on a first surface (circuit forming surface) of first and second opposite surfaces of the semiconductor chip, and a conductive wire for electrically connecting the electrode of said semiconductor chip with the interconnection of said substrate, said interconnection having a plurality of connecting pads arranged from the peripheral side toward the inner side of said substrate.Type: GrantFiled: June 6, 2002Date of Patent: January 4, 2005Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Tsugihiko Hirano, Hidemi Ozawa
-
Patent number: 6486415Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.Type: GrantFiled: January 16, 2001Date of Patent: November 26, 2002Assignee: International Business Machines CorporationInventors: Lisa J. Jimarez, Miguel A. Jimarez, Voya R. Markovich, Cynthia S. Milkovich, Charles H. Perry, Brenda L. Peterson
-
Patent number: 6448505Abstract: A substrate for mounting an optical component includes a first groove formed in a surface of a substrate, a second groove formed in the surface of the substrate, the second groove having a depth greater than the first groove. In the present invention, the first groove and the second groove are related to each other by the following equation, (2D sin &thgr;)/R≧C where D denotes a depth of the first groove, &thgr; denotes an angle between a horizontal plane and a slanted surface of the first groove (0°<&thgr;<90°), R=F/E (E denotes an etching rate of a slanted surface of the first groove, F denotes an etching rate of a bottom surface of the groove, C denotes a top opening width of the groove.Type: GrantFiled: October 26, 2000Date of Patent: September 10, 2002Assignee: Kyocera CorporationInventors: Michiaki Hiraoka, Keiko Nakashima, Koji Takemura
-
Patent number: 6369332Abstract: A metal-base multilayer circuit substrate which includes a metal plate and a circuit substrate bonded thereon by a first insulating adhesive layer containing at least one of metal oxides and/or at least one of metal nitrides with a heat resistance of at most 2.5° C./W.Type: GrantFiled: June 13, 2000Date of Patent: April 9, 2002Assignee: Denki Kagaku Kogyo Kabushiki KaishaInventors: Toshiki Saitoh, Naomi Yonemura, Tomohiro Miyakoshi, Makoto Fukuda
-
Patent number: 6342672Abstract: A superconducting apparatus includes a cryogenic chamber, superconducting equipment contained in the cryogenic chamber and a lead secured to the cryogenic chamber and connected to the superconducting equipment. A structured member for a prevention of an electric discharge is provided between the lead and an area for securing the lead of the cryogenic chamber. The structured member for the prevention of electric discharge may be a laminate of a conducting layer and a insulating layer having recoverable and non-recoverable insulation, and have an effect of shielding the corresponding lead from electromagnetic noises.Type: GrantFiled: February 9, 1995Date of Patent: January 29, 2002Assignee: Canon Kabushiki KaishaInventors: Norio Kaneko, Tamaki Kobayashi
-
Patent number: 6342680Abstract: A lead-free super-highly conductive plastic is formed of a conductive resin composition which includes a thermoplastic resin, a lead-free solder that melts during plasticization, and metal powder or a mixture of metal powder and metal short fibers that promotes the fine dispersion of particles of the lead-free solder within the thermoplastic resin. In the lead-free super-highly conductive plastic, since particles of the lead-free solder are connected with each other via solder melted within the plastic, the particles of the lead-free solder are mutually joined, so that high conductivity is attained.Type: GrantFiled: February 20, 1998Date of Patent: January 29, 2002Assignee: Japan Science and Technology CorporationInventors: Takeo Nakagawa, Hiroyuki Noguchi
-
Patent number: 6329608Abstract: A flip-ship structure having a semiconductor substrate including an electronic device formed thereon, a contact pad on said semiconductor substrate electrically connected to said electronic device, a passivation layer on said semiconductor substrate and on said contact pad wherein said passivation layer defines a contact hole therein exposing a portion of said contact pad, an under-bump metallurgy structure on said passivation layer electrically contacting said portion of said contact pad that is exposed; and a solder structure on said under-bump metallurgy structure opposite said semiconductor substrate, said solder structure including an elongate portion on said elongate portion of said metallurgy structure opposite said contact pad and an enlarged width portion on said enlarged width portion of said metallurgy structure opposite said passivation layer.Type: GrantFiled: April 5, 1999Date of Patent: December 11, 2001Assignee: Unitive International LimitedInventors: Glenn A. Rinne, Joseph Daniel Mis
-
Patent number: 6326561Abstract: A thin-film multilayer wiring board with first and second metallic wiring layers formed on a substrate and an organic insulating layer interposed between the metallic wiring layers. The insulating layer has the first metallic wiring layer and via holes in a thickness of the insulating layer. The lands of the first and second metallic wiring layers are electrically connected by via studs which are made of a conductive metal filled in the via holes.Type: GrantFiled: July 3, 1996Date of Patent: December 4, 2001Assignee: HItachi, Ltd.Inventors: Ryuji Watanabe, Takeyuki Itabashi, Osamu Miura, Akio Takahashi, Yukio Ookoshi, Hitoshi Suzuki, Masahiro Suzuki, Tsutomu Imai