Abstract: A pixel array may include a group of time-of-flight (ToF) sensors. The pixel array may include an image sensor comprising a group of pixel sensors. The image sensor may be arranged among the group of ToF sensors such that the image sensor is adjacent to each ToF sensor in the group of ToF sensors.

Abstract: A tunneling device includes a first semiconductor portion disposed on a first oxide substrate, a second semiconductor portion disposed on the first semiconductor portion, and an intermediate layer disposed between the first semiconductor portion and second semiconductor portion. The intermediate layer is a natural oxide film obtained by naturally oxidizing one surface of the second semiconductor portion for a predetermined time.

Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor over the first oxide; a first insulator over the first conductor; a second insulator over the second conductor; a second oxide provided over the first oxide and being in contact with the side surface of the first conductor and the side surface of the second conductor; a third oxide provided over the second oxide and including regions in contact with the side surface of the first insulator and the side surface of the second insulator; a third insulator over the third oxide; and a third conductor over the third insulator.

Abstract: The present application relates to an LED epitaxial structure and the preparation method and application thereof. The LED epitaxial structure comprises a first multiple-quantum-well light-emitting layer and a second multiple-quantum-well light-emitting layer. The first multiple-quantum-well light-emitting layer comprises a first shoes layer, a first well layer, a first cap layer, and a first Barrier layer epitaxially grown from bottom to top in sequence. The second multiple-quantum-well light-emitting layer comprises a second shoes layer, a second well layer, a second cap layer, and a second Barrier layer epitaxially grown from bottom to top in sequence. The technical solutions disclosed in the present application can solve the problem that the 365 nm to 375 nm wave band LED would emit yellow light.

Abstract: A device includes a first vertical stack of nanostructures over a substrate, a second vertical stack of nanostructures over the substrate, a wall structure between and in direct contact with the first and second vertical stacks, a gate structure wrapping around three sides of the nanostructures and a source/drain region beside the first vertical stack of nanostructures.

Abstract: The photoelectric conversion device includes a semiconductor layer provided with an avalanche photodiode, and an interconnection structure layer provided on a side of a first surface of the semiconductor layer. The interconnection structure layer includes an interconnection structure made of a metal material and overlapping with the avalanche multiplication region of the avalanche photodiode in a plan view. The interconnection structure includes a first interconnection, a second interconnection disposed farther from the first surface than the first interconnection, and a contact electrode electrically connecting the first interconnection and the second interconnection. An opening is provided in the first interconnection in a portion overlapping with the avalanche multiplication region in the plan view. The second interconnection is disposed so as to overlap an entire of the opening in the plan view. The contact electrode is arranged around the opening in the plan view.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

Abstract: The present disclosure relates to an image sensor having an epitaxial deposited photodiode structure surrounded by an isolation structure, and an associated method of formation. In some embodiments, a first epitaxial deposition process is performed to form a first doped EPI layer over a substrate. The first doped EPI layer is of a first doping type. Then, a second epitaxial deposition process is performed to form a second doped EPI layer on the first doped photodiode layer. The second doped EPI layer is of a second doping type opposite from the first doping type. Then, an isolation structure is formed to separate the first doped EPI layer and the second photodiode as a plurality of photodiode structures within a plurality of pixel regions. The plurality of photodiode structures is configured to convert radiation that enters from a first side of the image sensor into an electrical signal.

Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one cationic surfactant having at least one nitrogen atom in the molecule. The slurry includes at least one liquid carrier, at least one abrasive and at least one pH adjusting agent, and has a pH of less than 7.0. The polishing method includes using the slurry composition with the cationic surfactant to polish a conductive layer. The integrated circuit comprises a block layer comprising the cationic surfactant between a sidewall of the conductive plug and an interlayer dielectric layer.

Abstract: A semiconductor device including a cell active pattern; a cell gate structure connected to the cell active pattern; a peripheral active pattern; a peripheral gate structure connected to the peripheral active pattern; a conductive pattern connected to the peripheral active pattern, the cell gate structure, or the peripheral gate structure; a capacitor structure electrically connected to the cell active pattern; an interlayer insulating layer surrounding the capacitor structure; and a peripheral contact connected to the conductive pattern while extending through the interlayer insulating layer, wherein the interlayer insulating layer includes a first material layer contacting the capacitor structure, and a second material layer on the first material layer, the peripheral contact includes a first portion contacting the first material layer, and a second portion contacting the second material layer, and a maximum width of the first portion is greater than a minimum width of the second portion.

Abstract: The distance between an upper end of a light-shielding portion and a photoelectric conversion layer is longer than the distance between the lower surface of a light-shielding film and the photoelectric conversion layer. The distance between a lower end of the light-shielding portion and the photoelectric conversion layer is shorter than the distance between the lower surface of the light-shielding film and the photoelectric conversion layer. In a plane including the light-shielding film and the light-shielding portion, an opening defined by the light-shielding portion and a gap between the light-shielding portion and the light-shielding film are provided, and the width of the gap is smaller than the width of the opening.

Abstract: An electronic device includes: a substrate including a first region and a second region, wherein the first region is in a middle position, and the second region is closer to an edge of the substrate than the first region; a first active layer disposed on the substrate and in the second region; a conducting electrode disposed on the substrate and in the second region, wherein the conducting electrode electrically connects to the first active layer and extends along a first direction; and a conductive layer disposed on the substrate and in the second region, wherein the conductive layer includes an opening, wherein a minimum distance from an edge of the opening to the first active layer along the first direction is different from a minimum distance from another edge of the opening to the first active layer along a second direction different from the first direction.

Abstract: The present disclosure relates to an image sensor having an epitaxial deposited photodiode structure surrounded by an isolation structure, and an associated method of formation. In some embodiments, a first epitaxial deposition process is performed to form a first doped EPI layer over a substrate. The first doped EPI layer is of a first doping type. Then, a second epitaxial deposition process is performed to form a second doped EPI layer on the first doped EPI layer. The second doped EPI layer is of a second doping type opposite from the first doping type. Then, an isolation structure is formed to separate the first doped EPI layer and the second doped EPI layer as a plurality of photodiode structures within a plurality of pixel regions. The plurality of photodiode structures is configured to convert radiation that enters from a first side of the image sensor into an electrical signal.

Abstract: A light-emitting element includes a first electrode, a second electrode, a light-emitting layer, a hole injection layer provided between the first electrode and the light-emitting layer, and a hole transport layer provided between the hole injection layer and the light-emitting layer, wherein an insulator layer is provided between the hole injection layer and the hole transport layer. The hole injection layer, the insulator layer, and the hole transport layer each include a compound including one or more types of a cation and one or more types of an anion, the anion includes a group 15 or group 16 element of the periodic table, and an average oxidation number of cations in the insulator layer is greater than an average oxidation number of cations in the hole transport layer and less than an average oxidation number of cations in the hole injection layer.

Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation the same. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. Two protection layers sequentially surround a sidewall of the MTJ. The two protection layers have etch selectivity over one another.

Abstract: A semiconductor structure includes a gate structure over a substrate. The structure also includes a source/drain epitaxial structure formed on opposite sides of the gate structure. The structure also includes a contact structure formed over the gate structure. The structure also includes a metal layer formed over the contact structure. The structure also includes a cap layer formed over the metal layer. The structure also includes a first etch stop layer including a metal compound formed over the cap layer. The structure also includes a second etch stop layer including nitrogen formed over the first etch stop layer. The structure also includes a via structure that passes through the first etch stop layer and the second etch stop layer. The bottom surface of the cap layer is level with the bottom surface of the first etch stop layer.

Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation the same. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. Two protection layers sequentially surround a sidewall of the MTJ. The two protection layers have etch selectivity over one another.

Abstract: In an embodiment, a device includes: an isolation region; nanostructures protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.

Abstract: Structures and formation methods of a semiconductor structure are provided. The semiconductor structure includes an insulating layer covering a device region and an alignment mark region of a semiconductor substrate. A conductive feature is formed in the insulating layer and corresponds to the device region. An alignment mark structure is formed in the first insulating layer and corresponds to the alignment mark region. The alignment mark structure includes a first conductive layer, a second conductive layer covering the first conductive layer, and a first magnetic tunnel junction (MTJ) stack layer covering the second conductive layer. The first conductive layer and the conductive feature are made of the same material.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a bottom isolation feature formed over the substrate. The semiconductor structure also includes a bottom semiconductor layer formed over the bottom isolation feature and nanostructures formed over the bottom semiconductor layer. The semiconductor structure also includes a source/drain structure attached to the nanostructures and covering a portion of the bottom isolation feature.