Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

Abstract: A manufacturing method for a semiconductor chip includes: preparing a GaN wafer; producing a processed wafer by forming an epitaxial film on a surface of the GaN wafer to have chip formation regions adjacent to a first surface of the processed wafer; forming a first surface-side element component of a semiconductor element in each chip formation region; forming a wafer transformation layer along a planar direction of the processed wafer by irradiating an inside of the processed wafer with a laser beam; dividing the processed wafer at the wafer transformation layer into a chip formation wafer and a recycle wafer; extracting a semiconductor chip from the chip formation wafer; and after the preparing the GaN wafer and before the dividing the processed wafer, irradiating an inside of the gallium nitride wafer or the processed wafer with a laser beam to form a mark by deposition of gallium.

Abstract: A display device capable of improving a light emission efficiency includes a plurality of insulating films disposed on a substrate, a trench exposing side surfaces of the plurality of insulating films, a first alignment electrode disposed on the side surfaces of the plurality of insulating films exposed by the trench, a second alignment electrode disposed so as to be surrounded by the first alignment electrode, and a light-emitting device connected to the first and second alignment electrodes and disposed between the first and second alignment electrodes within the trench, thereby improving a light emission efficiency.

Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

Abstract: A complementary metal oxide semiconductor (CMOS) device includes a transistor of a first type formed over a first substrate, and a transistor of a second type formed over a second substrate. The CMOS device is formed when the transistor of the first type formed on the first substrate is bonded to the transistor of the second type formed over the second substrate.

Abstract: An epitaxial structure including at least a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a P-type aluminum indium gallium nitride layer is provided. The nucleation layer is formed on the substrate; the buffer layer is formed on the nucleation layer; the channel layer is formed on the buffer layer; the barrier layer is formed on the channel layer; and the P-type aluminum indium gallium nitride layer is formed on the barrier layer. The material of the P-type aluminum indium gallium nitride layer is AlInGaN with a P-type dopant, in which the contents of Al, In and Ga all change stepped-periodically or stepped-periodical-gradually in the thickness direction, and the doping concentration of the P-type dopant changes stepped-periodically or stepped-periodical-gradually in the thickness direction.

Abstract: A low refractive layer and a display device are provided. The display device includes a plurality of light-emitting elements, a color conversion layer on the light-emitting elements, and a low refractive layer on the color conversion layer, wherein the low refractive layer includes a monomer represented by Formula 1. In Formula 1, R1 and R3 may each independently be a substituted or unsubstituted alkyl group or hydrogen, R2 may be a substituted or unsubstituted alkyl group having two or more carbon atoms, Xa, Xb, and Xc may each independently be a curable functional group, and n and m may each independently be a natural number in a range of 1 to 5.

Abstract: An imaging device includes a photoelectric conversion region that converts incident light into electric charge. The imaging device includes a first readout circuit coupled to the photoelectric conversion region at a first location, and a second readout circuit including a portion coupled to the photoelectric conversion region at a second location. The second readout circuit is configured to control the first readout circuit. The first location and the second location are on a same side of the photoelectric conversion region.

Abstract: A semiconductor device includes a substrate with first and second regions separated from each other, a laminate structure including at least one sacrificial layer and at least one active layer alternately stacked on the substrate, a first isolation insulating layer on the laminate structure on the first region, a second isolation insulating layer on the laminate structure on the second region, the second isolation insulating layer having a same thickness as the first isolation insulating layer, a first upper active pattern spaced apart from the first isolation insulating layer, a first gate electrode surrounding at least a portion of the first upper active pattern, a second upper active pattern spaced apart from the second isolation insulating layer, and a second gate electrode surrounding at least a portion of the second upper active pattern, wherein top surfaces of the first and second isolation insulating layers are at different heights.

Abstract: A network state tracking system tracks the state of a network and recommends an action when the state of the network changes. The network state tracking system detects one or more nodes on the network and generates one or more snapshots of the network. The snapshots are generated by obtaining first and second status data from the nodes and detecting whether a change in the network has occurred based on the status data. The snapshots are generated based on the first and second status data when a change in the network is detected. The snapshots are then used to train a machine learning model to recommend an action to take when a change in the network occurs.

Abstract: A detector may be provided with a sensing element or an array of sensing elements, each of the sensing elements may have a corresponding gain element. A substrate may be provided having a sensing element and a gain element integrated together. The gain element may include a section in which, along a direction perpendicular to an incidence direction of an electron beam, a region of first conductivity is provided adjacent to a region of second conductivity, and a region of third conductivity may be provided adjacent to the region of second conductivity. The sensing element may include a section in which, along the incidence direction, a region of fourth conductivity is provided adjacent to an intrinsic region of the substrate, and the region of second conductivity may be provided adjacent to the intrinsic region.

Abstract: Embodiments of three-dimensional (3D) memory devices formed by bonded semiconductor devices and methods for forming the same are disclosed. In an example, a method for forming a semiconductor device is disclosed. The method includes the following operations. First, an insulating material layer can be formed over a substrate. In an example, single-crystalline silicon is not essential to the substrate. The insulating material layer can be patterned to form an isolation structure and a plurality of trenches in the isolation structure. A semiconductor material can be deposited to fill up the plurality of trenches to form a plurality of array-base regions in the isolation structure, the isolation structure insulating the plurality of array-base regions from one another. Further, a plurality of memory arrays can be formed over the plurality of array-base regions, and an insulating structure can be formed to cover the plurality of memory arrays and the plurality of array-base regions.

Abstract: A semiconductor device manufacturing method includes loading a semiconductor substrate into a chamber, the semiconductor substrate including a silicon oxide film, depositing a seed layer on the silicon oxide film by supplying a first silicon source material, supplying a purge gas on the seed layer, depositing a protective layer on the seed layer by repeating a first cycle, the first cycle including supplying a base source material layer and subsequently supplying the first silicon source material, and depositing a silicon nitride film on the protective layer by repeating a second cycle, the second cycle including supplying a second silicon source material and subsequently supplying a nitrogen source material.

Abstract: A semiconductor device includes a first source/drain, a second source/drain isolated from direct contact with the first source/drain in a horizontal direction, a channel extending between the first source/drain and the second source/drain, a gate surrounding the channel, an upper inner spacer between the gate and the first source/drain and above the channel, and a lower inner spacer between the gate and the first source/drain and under the channel, in which the channel includes a base portion extending between the first source/drain and the second source/drain, an upper protrusion portion protruding upward from a top surface of the base portion, and a lower protrusion portion protruding downward from a bottom surface of the base portion, and a direction in which a top end of the upper protrusion portion is isolated from direct contact with a bottom end of the lower protrusion portion is oblique with respect to a vertical direction.

Abstract: An electronic device may include an IC, a grid array substrate, and a multi-level interposer coupled between the IC and the grid array substrate. The multi-level interposer may have dielectric layers, and a sequence of metal levels carried by respective dielectric layers, and an RF sloped via including a sloped metal signal layer extending from a first metal level, through a second metal level, and to a third metal level, and a respective sloped lateral metal ground layer adjacent each side of the sloped metal signal layer.

Abstract: A semiconductor structure includes a substrate including a device region, a peripheral region surrounding the device region, and a transition region disposed between the device region and the peripheral region. An epitaxial layer is disposed on the device region, the peripheral region, and the transition region. A first portion of the epitaxial layer on the peripheral region has a poly-crystal structure.

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

Abstract: A light-emitting device with a long lifetime is provided. In a light-emitting device that includes an EL layer between a pair of electrodes, a light-emitting layer included in the EL layer has a functional stacked-layer structure, whereby the efficiency and reliability of the light-emitting device can be increased.

Abstract: A memory cell includes a bit line and a plate line that are spaced apart from each other and vertically oriented in a first direction; a transistor provided with an active region that is laterally oriented in a second direction crossing the bit line and includes a first active cylinder, a second active cylinder, and at least one channel portion oriented laterally between the first active cylinder and the second active cylinder; a word line extending in a third direction while surrounding the at least one channel portion of the active region; and a capacitor oriented laterally in the second direction between the active region and the plate line.

Abstract: The present invention relates to technology for fabricating a gallium nitride substrate using an ion implantation process to which a self-separation technique is applied. According to the present invention, a method of fabricating a gallium nitride substrate may include a step of forming a first gallium nitride layer on a substrate, a step of implanting hydrogen ions into the first gallium nitride layer to form a separation layer, a step of grinding the edges of the substrate, the first gallium nitride layer, and the separation layer, a step of forming a second gallium nitride layer on the first gallium nitride layer having a ground edge, and a step of self-separating the second gallium nitride layer from the first gallium nitride layer having a ground edge.