Abstract: Method for time synchronization in a network between at least one master and at least one slave, which is an interrupt-capable network component and uses a timer, which accesses a slave time to generate at least one interrupt recurring at a predefined cycle duration, at a respective trigger point in time that is synchronized with the slave time. When a synchronization message arrives, a time offset between the master time and the slave time is determined in the slave, and a time fraction is determined from the time offset, which corresponds to an integer multiple of the predefined cycle duration of the at least one interrupt. An interrupt offset is then determined from the time fraction and the time offset. At least one time jump is carried out by a synchronization unit in the slave to correct the time offset.

Abstract: An apparatus and method for timing skew calibration. For example, the apparatus may include an analog-to-digital conversion circuit configured to sample an input signal based on a clock signal and convert the sampled input signal into a digital code, a skew detection circuit configured to calculate a first sum of standard deviations for respective levels of the digital code, compare the first sum of the standard deviations with a previously calculated second sum of standard deviations, and select a smaller value from among the first sum and the second sum, and a compensation circuit configured to compensate for a skew of the clock signal based on the selected one of the first sum and the second sum.

Abstract: The present invention relates to latency compensation for image processing devices. In order to assign overlay data to frames of a raw image stream (210), past frames within a selection of frames of the raw image stream are considered, which past frames already underwent image processing. A current frame of the raw image stream (210) is compared to the past frames contained in the selection of frames, and that one of the past frames is identified that is most similar to the current frame. Overlay data from the identified past frame are chosen and assigned to the current frame. Thus, the current frame can be presented together with the assigned overlay data chosen from the most similar past frame and without the need to wait for the result of a computationally expensive and time-consuming image processing of the current frame.

Abstract: A virtual reality or mixed reality system configured to preform object detection using a monocular camera. The system configured to make the user aware of the detected objects by showing edges or lines of the object within a virtual scene. Thus, the user the user is able to avoid injury or collision while immersed in the virtual scene. In some cases, the system may also detect and correct for drift in the six degree of freedom pose of the user using corrections based on the current motion of the users.

Abstract: Aspects of the disclosure provide for an apparatus. In some examples, the apparatus includes a clock generator, a clock data recovery (CDR) circuit, a state machine, and an adder. The clock generator is configured to determine a sampling clock based on a received input clock and a clock offset. The CDR circuit is configured to determine a phase of the input clock and determine CDR codes based on the determined phase and sampled data. The state machine is configured to record a first CDR code of the CDR codes at a first time, record a second CDR code of the CDR codes at a second time subsequent to the first time, and determine a calibrated offset based on the first CDR code and the second CDR code. The adder is configured to determine the clock offset according to the CDR codes and the calibrated offset.

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

Abstract: An electronic device according to an embodiment may include: a battery; a connector including multiple pins; and at least one processor, and wherein the at least one processor is configured to: identify an external electronic device electrically connected through the connector, identify, among at least two supportable current values, a current value of power to be supplied to the external electronic device, and supply power of the battery to the external electronic device through the connector based on the identified current value.

Abstract: A system and method are described herein for estimating power usage of various components of a CPU and controlling voltage regulators based on the estimated power usage. The power estimates may be based on digital power meter readings at each component, on voltage information from a voltage regulator, and on other power information. This power information is transmitted over a mesh interconnect disposed throughout the CPU such that power estimation can be accurately calculated and used to control voltage regulators without being limited by external bus speeds. More of the power management processes and components may be disposed on the CPU and connected to the mesh interconnect. These power management processes include various calibrations, adjustments, and limits so as efficiently manage and use the more rapidly processed power estimations.

Abstract: A disclosed method for improving latency or power consumption may include (i) receiving, at a power-state processing circuit, a power-state signal indicating whether a processing unit is entering a low-power-state, (ii) transmitting, in response to the power-state signal indicating that the processing unit is entering the low-power-state, a control signal from the power-state processing circuit to a latching circuit, and (iii) storing, by the latching circuit and in response to the control signal, a state of an input/output pad that is coupled to the processing unit. Various other apparatuses, systems, and methods are also disclosed.

Abstract: An information interaction method, a computer-readable storage medium and a communication terminal are disclosed. The information interaction method is applied to a local terminal, and includes: in a process of a video call with a remote terminal, in response to a first interaction instruction, performing split-screen display on a display screen of the local terminal to form at least a first split screen for displaying an interface of the video call and a second split screen for displaying a shopping interface; in response to a first selection instruction, acquiring an image of a commodity corresponding to the first selection instruction, with the first selection instruction being an instruction of selecting the commodity from the shopping interface; and displaying a synthesized image obtained by performing image synthesis on the image of the commodity and at least a part of images in the interface of the video call.

Abstract: The disclosure provides a microcontroller which has an internal timing device for generating an internal clock signal, at least one terminal contact for receiving an external clock signal, a clock changing device and a timer module, which is electrically conductively connected to the at least one terminal contact and to the internal timing device and, after the microcontroller has been switched on, is set up to determine a frequency of the external clock signal by means of the clock signal, and to determine at least one parameter by means of which the clock changing device can be set up to change the external clock signal into a useful clock signal with a predefined frequency.

Abstract: An information processing system includes an execution block computational strength data area, a roofline model data storage unit, a computational strength data acquisition unit, and a performance power control unit. The execution block computational strength data area holds computational strength data of each execution block constituting an arithmetic application that operates in a computer system including a processor and a main storage apparatus. The roofline model data storage unit holds a roofline model corresponding to an operation frequency and the number of cores of the processor, and an operation frequency of the main storage apparatus. The computational strength data acquisition unit acquires computational strength data of each execution block. The performance power control unit controls an operation frequency and the number of cores of the processor and an operation frequency of the main storage apparatus based on the roofline model and the computational strength data of each execution block.

Abstract: Systems and methods are provided herein for detecting key words provided by ancillary devices and acquiring virtual objects based on the detected key words. This may be accomplished by a system displaying an augmented reality view to a user and detecting a received message. The system can determine whether a portion of the message corresponds to an augmented reality object. In response to detecting that the portion of the message corresponds to the augmented reality object, the system can display the augmented reality object in the augmented reality view in a first format. The first format can be based on the environment around the user.

Abstract: The present invention provides a guide display device capable of recognizing a feature in a work area while distinguishing whether the feature is a moving body or not. In a guide display device of a crane, 3D maps are created for continuous frames; an altitude value for each grid in a 3D map that is created at time closest to the current time is obtained as a first altitude value; altitude values for respective corresponding grids in a predetermined number of 3D maps other than the 3D map that is created at time closest to the current time are obtained, and the average of the altitude values is calculated as a second altitude value; and it is determined that the feature is a moving body when the difference between the first altitude value and the second altitude value exceeds a predetermined threshold.

Abstract: Described herein are systems and methods for the simulation of the upper airway of a subject. One embodiments provides a method (100) including the initial step (101) of receiving one or more tomographic images of the subject. At step (102) a three dimensional geometric model of the upper airway is generated from the one or more tomographic images. The geometric model includes a network of interconnected deformable mesh elements collectively defining a fluid domain (310) and a solid domain (320). The solid domain (320) defining a single unitary model of the entire upper airway region segmented into a plurality of predefined geometric regions, each being defined by one or more common anatomical parameters. At step (103), a computer simulation is performed on the geometric model to simulate behaviour of the upper airway when the subject is positioned in a predefined position.

Abstract: Various aspects of methods, systems, and use cases include coordinating actions at an edge device based on power production in a distributed edge computing environment. A method may include identifying a long-term service level agreement (SLA) for a component of an edge device, and determining a list of resources related to the component using the long-term SLA. The method may include scheduling a task for the component based on the long-term SLA, a current battery level at the edge device, a current energy harvest rate at the edge device, or an amount of power required to complete the task. A resource of the list of resources may be used to initiate the task, such as according to the scheduling.

Abstract: A Power-over-Ethernet (POE) powered device (PD) may be coupled to two power sourcing equipments (PSEs), a PSE and an additional PSE. The PSE may exchange a transport layer protocol communications with the additional PSE. The communications comprising a first communication from the PSE to the additional PSE indicative of a PoE configuration of the PSE and a second communication from the additional PSE to the PSE indicative of a PoE configuration of the additional PSE. The PSE may create a power availability table based on the communications. The PSE may detect occurrence of an event comprising at least one of a change in the power availability table or a change in ability of the PSE to provide power to the PD. On occurrence of the event, the PSE may send additional communications to the additional PSE, requesting to adjust its power allotment for the PD.

Abstract: Systems and methods for managing performance in heterogenous computing platforms of IHS (Information Handling Systems) are described. In an illustrative, non-limiting embodiment, a heterogeneous computing platform includes devices and a memory storing firmware instructions. Based on execution of these firmware instructions by a respective device, a corresponding firmware service is provided such that one of the devices operates as an orchestrator. The orchestrator receives reports of changes in context of operation of the IHS by a user and based on the change in user context, determines responsiveness settings that are mapped to the reported user context, where the responsiveness settings adjust thread management policies by one or more processors of the heterogeneous computing platform. The orchestrator configures the one or more processors of the heterogeneous computing platform based on the responsiveness settings, and thus adjusts the performance of the IHS in response to the change in user context.

Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

Abstract: An image processing method includes: acquiring a first image containing a target object; inputting the first image into an image processing model to obtain a second image, the second image being a mask image of the target object in the first image, a value for each pixel in the second image being in a range of 0 to 1, inclusive ([0, 1]), and the range of 0 to 1, inclusive ([0, 1]) indicating a degree of relation between each pixel in the second image and a pixel in the target object; fusing the first image and a background image according to the second image to obtain a fused image; and providing a first interface and displaying the fused image on the first interface.