Abstract: The disclosed method includes acquiring sample models and marking sample feature points; selecting target feature points and regional points on bones; transforming the target feature points and the regional points, and registering the target feature points with the sample feature points; formulating a strategy for assigning impact factors to the sample models, linearly combining all sample models to construct an initial model, and determining initial feature points corresponding to the target feature points in the initial model; adjusting the strategy according to the distance between initial feature points and the target feature points, selecting the strategy corresponding to the minimum distance as an optimal strategy, and determining an optimal initial model; determining a matching point corresponding to each regional point in the optimal initial model, and calculating a transformation relationship; and transmitting all points of the optimal initial model according to the transformation relationship to obt

Abstract: A clock sending apparatus and method, and a clock receiving apparatus and method are disclosed. The clock sending apparatus may include, an input unit configured to input a first and second input clocks; a sampling unit configured to acquire a first and second sampling clocks, and determine a first frequency control word according to the first and second sampling clocks, the first frequency control word is indicative of a relationship between the first and second sampling clocks, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to a preset rule; and a sending unit configured to generate a clock signal according to the first input clock and send the clock signal that carries at least the first frequency control word to a receiving side.

Abstract: Systems and methods for burst power limit control in heterogenous computing platforms are described. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include: a heterogeneous computing platform having a plurality of devices; and a memory coupled to the heterogeneous computing platform, where the memory includes firmware instructions that, upon execution by at least one of the plurality of devices, causes the at least one device to operate as an orchestrator configured to: compare a current power level used by a selected device against a burst power limit; and in response to a determination that the current power level exceeds the burst power limit, control the selected device to reduce the current power level.

Abstract: Disclosed herein are techniques to coordinate power management between a platform and a panel. Provided are apparatuses, techniques, and circuitry to determine whether to initiate power management features in a panel and send a signal from a platform to the panel including an indication that no frame updates are expected and power management functions can be initiated.

Abstract: Disclosed embodiments are related to techniques for powering compute platforms in low temperature environments. Embodiments include a preheating stage that is added to a power up sequence. The preheating stage may include a force-on stage and a force-offstage. During the force-on stage, all power rails of target components are forced to an ON state so that the target components consume current. When a target operating temperature is reached, the power rails of the target components are turned off, which causes the target components to revert back to their initial (pre-boot) state allowing the normal boot process to take place. Since the target components are now heated up, the boot process can execute faster than when the target components were cold. Other embodiments may be described and/or claimed.

Abstract: A method includes receiving, from a subscriber device, a request including virtual region characteristics and an occupancy threshold, and determining, using image data captured by a camera and the virtual region characteristics, a virtual region corresponding to a portion of a physical region within a field of view of the camera. The virtual region is smaller than the physical region. The method also includes determining, using the image data, an occupancy of the virtual region and determining that the occupancy of the virtual region satisfies the occupancy threshold. In response to determining that the occupancy of the virtual region satisfies the occupancy threshold, the method also includes generating a notification to the subscriber device.

Abstract: A sensor image generated based on data obtained from a remote sensor is displayed on a display of a terminal communicating with the remote sensor. The remote sensor includes a sensor mounted on a moving body. The sensor image includes a moving body image representing an image generated based on data obtained from the sensor mounted on the moving body. In the moving body image, right and left regions are set with respect to front of the moving body. Right and left recognition assistances are superimposed respectively on the right and left regions. A color of the right recognition assistance is different from a color of the left recognition assistance.

Abstract: A method for training a three-dimensional face reconstruction model includes inputting an acquired sample face image into a three-dimensional face reconstruction model to obtain a coordinate transformation parameter and a face parameter of the sample face image; determining the three-dimensional stylized face image of the sample face image according to the face parameter of the sample face image and the acquired stylized face map of the sample face image; transforming the three-dimensional stylized face image of the sample face image into a camera coordinate system based on the coordinate transformation parameter, and rendering the transformed three-dimensional stylized face image to obtain a rendered map; and training the three-dimensional face reconstruction model according to the rendered map and the stylized face map of the sample face image.

Abstract: Graphics processing system configured to perform ray tracing. Rays are bundled together and processed together. When differential data is needed by a shader, the data of a true ray in the bundle can be used rather than processing separate tracker rays.

Abstract: A system and method employing a precisely synchronized time in connection with a distributed hardware architecture are disclosed. Using an independent and trusted time signal and a second transition pulse signal, each resource in the distributed hardware architecture may be synchronized precisely to the same absolute time.

Abstract: Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage.

Abstract: Methods, systems and computer program products for in-application virtual object sharing include (i) responsive to a first acquiring a virtual object recognized by a software application, identifying a first user identifier associated with the first user, (ii) identifying a virtual object identifier associated with the virtual object, (iii) identifying a user group representing a plurality of users including the first user (iv) associating the virtual object identifier with one or more additional user identifiers associated with users within the user group, and (v) updating in a non-transitory memory, a profile corresponding to each user associated with the user group, that also has the virtual object identifier associated with a user identifier corresponding to said user, wherein said update to the profile is based on the properties of the virtual object.

Abstract: A method for generating a representation of a three-dimensional protective device includes accessing a scan of anatomical data of a target and identifying a reference model of a closest size or proportion to a size or proportion of the target. The method further includes creating a boundary of a three-dimensional protective device using the reference model and the scan of anatomical data of the target. Additionally, the method includes generating a representation of a continuous, three-dimensional surface of the three-dimensional protective device that corresponds to the scan of anatomical data and the reference model within the boundary of the three-dimensional protective device.

Abstract: Method for time synchronization in a network between at least one master and at least one slave, which is an interrupt-capable network component and uses a timer, which accesses a slave time to generate at least one interrupt recurring at a predefined cycle duration, at a respective trigger point in time that is synchronized with the slave time. When a synchronization message arrives, a time offset between the master time and the slave time is determined in the slave, and a time fraction is determined from the time offset, which corresponds to an integer multiple of the predefined cycle duration of the at least one interrupt. An interrupt offset is then determined from the time fraction and the time offset. At least one time jump is carried out by a synchronization unit in the slave to correct the time offset.

Abstract: An apparatus and method for timing skew calibration. For example, the apparatus may include an analog-to-digital conversion circuit configured to sample an input signal based on a clock signal and convert the sampled input signal into a digital code, a skew detection circuit configured to calculate a first sum of standard deviations for respective levels of the digital code, compare the first sum of the standard deviations with a previously calculated second sum of standard deviations, and select a smaller value from among the first sum and the second sum, and a compensation circuit configured to compensate for a skew of the clock signal based on the selected one of the first sum and the second sum.

Abstract: The present invention relates to latency compensation for image processing devices. In order to assign overlay data to frames of a raw image stream (210), past frames within a selection of frames of the raw image stream are considered, which past frames already underwent image processing. A current frame of the raw image stream (210) is compared to the past frames contained in the selection of frames, and that one of the past frames is identified that is most similar to the current frame. Overlay data from the identified past frame are chosen and assigned to the current frame. Thus, the current frame can be presented together with the assigned overlay data chosen from the most similar past frame and without the need to wait for the result of a computationally expensive and time-consuming image processing of the current frame.

Abstract: A system and method are described herein for estimating power usage of various components of a CPU and controlling voltage regulators based on the estimated power usage. The power estimates may be based on digital power meter readings at each component, on voltage information from a voltage regulator, and on other power information. This power information is transmitted over a mesh interconnect disposed throughout the CPU such that power estimation can be accurately calculated and used to control voltage regulators without being limited by external bus speeds. More of the power management processes and components may be disposed on the CPU and connected to the mesh interconnect. These power management processes include various calibrations, adjustments, and limits so as efficiently manage and use the more rapidly processed power estimations.

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

Abstract: An electronic device according to an embodiment may include: a battery; a connector including multiple pins; and at least one processor, and wherein the at least one processor is configured to: identify an external electronic device electrically connected through the connector, identify, among at least two supportable current values, a current value of power to be supplied to the external electronic device, and supply power of the battery to the external electronic device through the connector based on the identified current value.

Abstract: Aspects of the disclosure provide for an apparatus. In some examples, the apparatus includes a clock generator, a clock data recovery (CDR) circuit, a state machine, and an adder. The clock generator is configured to determine a sampling clock based on a received input clock and a clock offset. The CDR circuit is configured to determine a phase of the input clock and determine CDR codes based on the determined phase and sampled data. The state machine is configured to record a first CDR code of the CDR codes at a first time, record a second CDR code of the CDR codes at a second time subsequent to the first time, and determine a calibrated offset based on the first CDR code and the second CDR code. The adder is configured to determine the clock offset according to the CDR codes and the calibrated offset.