Patents Examined by Kamran Afshar
  • Patent number: 12147906
    Abstract: Methods, systems, and computer program products for localization-based test generation for individual fairness testing of AI models are provided herein. A computer-implemented method includes obtaining at least one artificial intelligence model and training data related to the at least one artificial intelligence model; identifying one or more boundary regions associated with the at least one artificial intelligence model based at least in part on results of processing at least a portion of the training data using the at least one artificial model; generating, in accordance with at least one of the one or more identified boundary regions, one or more synthetic data points for inclusion with the training data; and executing one or more fairness tests on the at least one artificial intelligence model using at least a portion of the one or more generated synthetic data points and at least a portion of the training data.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: November 19, 2024
    Assignee: International Business Machines Corporation
    Inventors: Diptikalyan Saha, Aniya Aggarwal, Sandeep Hans
  • Patent number: 12147892
    Abstract: Provided is an electronic apparatus. The electronic apparatus includes a memory and a processor. The processor is configured to apply a low rank approximation using a matrix decomposition for a first square matrix among a plurality of square matrices based on parameter values of a deep learning model, and obtain a first approximated matrix and a second approximated matrix for the first square matrix, obtain second approximated matrices for each of a plurality of remaining square matrices other than the first square matrix among the plurality of square matrices, based on the first approximated matrix for the first square matrix, and store the first approximated matrix the first square matrix and the second approximated matrices for each of the plurality of square matrices in the memory.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: November 19, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sejung Kwon, Baeseong Park, Dongsoo Lee
  • Patent number: 12141238
    Abstract: Discussed herein are devices, systems, and methods for classification using a clustering autoencoder. A method can include obtaining content to be classified by the DNN classifier, and operating the DNN classifier to determine a classification of the received content, the DNN classifier including a clustering classification layer that clusters based on a latent feature vector representation of the content, the classification corresponding to one or more clusters that are closest to the latent feature vector providing the classification and a corresponding confidence.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 12, 2024
    Assignee: Raytheon Company
    Inventors: Philip A. Sallee, James Mullen
  • Patent number: 12136039
    Abstract: Some embodiments provide a method for training multiple parameters of a machine-trained (MT) network subject to a sparsity constraint that requires a threshold portion of the parameters to be equal to zero. A first set of the parameters subject to the sparsity constraint are grouped into groups of parameters. For each parameter of a second set of the parameters subject to the sparsity constraint, the method determines an accuracy penalty associated with the parameter being set to zero. For each group of parameters in the first set of parameters, the method determines a minimum accuracy penalty for each possible number of parameters in the group being set to zero. The method uses the determined accuracy penalties to set to the value zero at least the threshold portion of the plurality of parameters.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: November 5, 2024
    Assignee: PERCEIVE CORPORATION
    Inventors: Eric A. Sather, Steven L. Teig
  • Patent number: 12112264
    Abstract: A device which comprises an array of resistive processing unit (RPU) cells, first control lines extending in a first direction across the array of RPU cells, and second control lines extending in a second direction across the array of RPU cells. Peripheral circuitry comprising readout circuitry is coupled to the first and second control lines. A control system generates control signals to control the peripheral circuitry to perform a first operation and a second operation on the array of RPU cells. The control signals include a first configuration control signal to configure the readout circuitry to have a first hardware configuration when the first operation is performed on the array of RPU cells, and a second configuration control signal to configure the readout circuitry to have a second hardware configuration, which is different from the first hardware configuration, when the second operation is performed on the array of RPU cells.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: October 8, 2024
    Assignee: International Business Machines Corporation
    Inventors: Malte Johannes Rasch, Tayfun Gokmen, Seyoung Kim
  • Patent number: 12106491
    Abstract: Embodiments of this application disclose a target tracking method performed at an electronic device. The electronic device obtains a first video stream and detects candidate regions within a current video frame in the first video stream. The electronic device then extracts, from the candidate regions, a deep feature corresponding to each candidate region and calculates a feature similarity for each candidate region and a deep feature of a target detected in a previous video frame. Finally, the electronic device determines, based on the feature similarity corresponding to the candidate region, that the target is detected in the current video frame. Target detection is performed in a range of video frames by using a target detection model, and target tracking is performed based on the deep feature, so that occurrence of cases such as a target tracking drift or loss can be effectively prevented, to ensure the accuracy of target tracking.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: October 1, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Hao Zhang, Zhiwei Niu
  • Patent number: 12079704
    Abstract: A system includes a data collection engine, a plurality of items including radio-frequency identification chips, a plurality of third party data and insight sources, a plurality of interfaces, client devices, a server and method thereof for preventing suicide. The server includes trained machine learning models, business logic and attributes of a plurality of patient events. The data collection engine sends attributes of new patient events to the server. The server can predict an adverse event risk of the new patient events based upon the attributes of the new patient events utilizing the trained machine learning models.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: September 3, 2024
    Assignee: Brain Trust Innovations I, LLC
    Inventor: David LaBorde
  • Patent number: 12067484
    Abstract: An example method of training a neural network includes defining hardware building blocks (HBBs), neuron equivalents (NEQs), and conversion procedures from NEQs to HBBs; defining the neural network using the NEQs in a machine learning framework; training the neural network on a training platform; and converting the neural network as trained into a netlist of HBBs using the conversion procedures to convert the NEQs in the neural network to the HBBs of the netlist.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 20, 2024
    Assignee: XILINX, INC.
    Inventors: Yaman Umuroglu, Nicholas Fraser, Michaela Blott, Kristof Denolf, Kornelis A. Vissers
  • Patent number: 12067479
    Abstract: Systems and methods for heterogenous hardware acceleration are disclosed. The systems and methods can include a neural network processing unit comprising compute tiles. Each of a first set of the compute tiles can include a first tensor array configured to support operations in a first number format. Each of a second set of the compute tiles can include a second tensor array configured to support operations in a second number format, the second number format supporting a greater range or a greater precision than the first number format, and a de-quantizer configured to convert data in the first number format to data in the second number format. The systems and methods can include neural network processing units, multi-chip hardware accelerators and distributed hardware accelerators including low-precision components for performing interference tasks and high-precision components for performing training tasks.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: August 20, 2024
    Assignee: T-Head (Shanghai) Semiconductor Co., Ltd.
    Inventor: Liang Han
  • Patent number: 12067485
    Abstract: Methods, systems, and non-transitory computer readable medium are provided for long short-term memory (LSTM) anomaly detection for multi-sensor equipment monitoring. A method includes training a LSTM recurrent neural network (RNN) model for semiconductor processing fault detection. The training includes generating training data for the LSTM RNN model and providing the training data to train the LSTM RNN model on first training input and first target output to generate a trained LSTM RNN model for the semiconductor processing fault detection. The training data includes the first training input and the first target output based on normal runs of manufacturing processes of semiconductor processing equipment. Another method includes providing input based on runs of manufacturing processes of semiconductor processing equipment to a trained LSTM RNN model; obtaining one or more outputs from the trained LSTM RNN model; and using the one or more outputs for semiconductor processing fault detection.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 20, 2024
    Assignee: Applied Materials, Inc
    Inventors: Sima Didari, Tianqing Liao, Harikrishnan Rajagopal
  • Patent number: 12056604
    Abstract: Layers of a deep neural network (DNN) are partitioned into stages using a profile of the DNN. Each of the stages includes one or more of the layers of the DNN. The partitioning of the layers of the DNN into stages is optimized in various ways including optimizing the partitioning to minimize training time, to minimize data communication between worker computing devices used to train the DNN, or to ensure that the worker computing devices perform an approximately equal amount of the processing for training the DNN. The stages are assigned to the worker computing devices. The worker computing devices process batches of training data using a scheduling policy that causes the workers to alternate between forward processing of the batches of the DNN training data and backward processing of the batches of the DNN training data. The stages can be configured for model parallel processing or data parallel processing.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 6, 2024
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Vivek Seshadri, Amar Phanishayee, Deepak Narayanan, Aaron Harlap, Nikhil Devanur Rangarajan
  • Patent number: 12045725
    Abstract: Some embodiments provide a method for training a network including layers that each includes multiple nodes. The method identifies a set of related layers of the network. Each node in one of the related layers has corresponding nodes in each of the other related layers. Each set of corresponding nodes receives a same set of inputs and applies different sets of weights to the inputs to generate an output. The method identifies an element-wise addition layer including nodes that each add outputs of a different set of corresponding nodes from the related layers to generate a sum. The method uses a set of outputs generated by the nodes of each related layer to determine batch normalization parameters specific to each layer of the set of related layers. The method uses data generated by the element-wise addition layer to determine batch normalization parameters for the set of related layers.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: July 23, 2024
    Assignee: PERCEIVE CORPORATION
    Inventors: Eric A. Sather, Steven L. Teig
  • Patent number: 12039432
    Abstract: An artificial neural network (ANN) apparatus can include processing component circuitry that receives linear inputs, and removes linearity from the one or more linear inputs based on an S-shaped saturating activation function that generates a continuous non-linear output. The neurons of the ANN comprise digital bit-wise components configured to transform the linear inputs into the continuous non-linear output.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: July 16, 2024
    Assignee: Infineon Technologies AG
    Inventor: Andrew Stevens
  • Patent number: 12033053
    Abstract: Embodiments of the invention may execute a NN by executing sub-tensor columns, each sub-tensor column including computations from portions of a layers of the NN, and each sub-tensor column performing computations entirely within a first layer of cache (e.g. L2 in one embodiment) and saving its output entirely within a second layer of cache (e.g. L3 in one embodiment). Embodiments may include partitioning the execution of a NN by partitioning the execution of the NN into sub-tensor columns, each sub-tensor column including computations from portions of layers of the NN, each sub-tensor column performing computations entirely within a first layer of cache and saving its output entirely within a second layer of cache.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: July 9, 2024
    Assignee: NEURALMAGIC, INC.
    Inventors: Alexander Matveev, Nir Shavit, Govind Ramnarayan
  • Patent number: 12020163
    Abstract: A method includes receiving a request to solve a problem defined by input information and applying a neural network to generate an answer to the problem. The neural network includes an input level, a manager level including a first manager, a worker level including first and second workers, and an output level. Applying the neural network includes implementing the input level to provide a piece of input information to the first manager; implementing the first manager to delegate portions of the piece of information to the first and second workers; implementing the first worker to operate on its portion of information to generate a first output; implementing the second worker to operate on its portion of information to generate a second output; and implementing the output level to generate the answer to the problem, using the first and second outputs. The method also includes transmitting a response comprising the answer.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: June 25, 2024
    Assignee: Bank of America Corporation
    Inventors: Garrett Thomas Botkin, Matthew Bruce Murray
  • Patent number: 12020160
    Abstract: A method, computer program product and system for generating a neural network. Initial neural networks are prepared, each of which includes an input layer containing one or more input nodes, a middle layer containing one or more middle nodes, and an output layer containing one or more output nodes. A new neural network is generated that includes a new middle layer containing one or more middle nodes based on the middle nodes of the middle layers of the initial neural networks.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: June 25, 2024
    Assignee: International Business Machines Corporation
    Inventor: Takeshi Inagaki
  • Patent number: 12014262
    Abstract: Disclosed herein are apparatus, method, and computer-readable storage device embodiments for implementing deconvolution via a set of convolutions. An embodiment includes a convolution processor that includes hardware implementing logic to perform at least one algorithm comprising a convolution algorithm. The at least one convolution processor may be further configured to perform operations including performing a first convolution and outputting a first deconvolution segment as a result of the performing the first convolution. The at least one convolution processor may be further configured to perform a second convolution and output a second deconvolution segment as a result of the performing the second convolution.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: June 18, 2024
    Assignee: SYNOPSYS, INC.
    Inventors: Tom Michiels, Thomas Julian Pennello
  • Patent number: 12001944
    Abstract: A mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine an optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: June 4, 2024
    Assignee: INTEL CORPORATION
    Inventors: Rajkishore Barik, Brian T. Lewis, Murali Sundaresan, Jeffrey Jackson, Feng Chen, Xiaoming Chen, Mike Macpherson
  • Patent number: 11995533
    Abstract: Some embodiments provide a method for executing a layer of a neural network, for a circuit that restricts a number of weight values used per layer. The method applies a first set of weights to a set of inputs to generate a first set of results. The first set of weights are restricted to a first set of allowed values. For each of one or more additional sets of weights, the method applies the respective additional set of weights to the same set of inputs to generate a respective additional set of results. The respective additional set of weights is restricted to a respective additional set of allowed values that is related to the first set of allowed values and the other additional sets of allowed values. The method generates outputs for the particular layer by combining the first set of results with each respective additional set of results.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: May 28, 2024
    Assignee: PERCEIVE CORPORATION
    Inventors: Eric A. Sather, Steven L. Teig
  • Patent number: 11954597
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for using embedded function with a deep network. One of the methods includes receiving an input comprising a plurality of features, wherein each of the features is of a different feature type; processing each of the features using a respective embedding function to generate one or more numeric values, wherein each of the embedding functions operates independently of each other embedding function, and wherein each of the embedding functions is used for features of a respective feature type; processing the numeric values using a deep network to generate a first alternative representation of the input, wherein the deep network is a machine learning model composed of a plurality of levels of non-linear operations; and processing the first alternative representation of the input using a logistic regression classifier to predict a label for the input.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: April 9, 2024
    Assignee: Google LLC
    Inventors: Gregory S. Corrado, Kai Chen, Jeffrey A. Dean, Gary R. Holt, Julian P. Grady, Sharat Chikkerur, David W. Sculley, II