Abstract: A scribe line structure is disclosed. The scribe line structure includes a semiconductor substrate having a die region, a die seal ring region, disposed outside the die region, a scribe line region disposed outside the die seal ring region and a dicing path formed on the scribe line region. Preferably, the center line of the dicing path is shifted away from the center line of the scribe line region along a first direction.

Abstract: An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside of the substrate. The MEMS mechanical structure is then released. A protective layer is formed on the frontside of the substrate. The protective layer is disposed on the released MEMS mechanical structure (e.g., protects the MEMS structure). The backside of the substrate is processed while the protective layer is disposed on the MEMS mechanical structure.

Abstract: A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second material layers having a different etching selectivity on a semiconductor substrate; forming an opening penetrating the plurality of first and second material layers; removing the first material layers exposed by the opening to form extended portions extending in a direction perpendicular to the semiconductor substrate from the opening; conformally forming a charge storage layer along a surface of the opening and the extended portions; and removing the charge storage layer formed on sidewalls of the second material layers to locally form the charge storage layer patterns in the extended portions.

Abstract: A transistor, an inverter including the transistor, and methods of manufacturing the inverter and the transistor. A gate insulating layer of the transistor has a charge trap region. A threshold voltage may be moved in a positive (+) direction by trapping charges in the charge trap region. The transistor may be an enhancement mode oxide thin-film transistor (TFT) and may be used as an element of the inverter.

Abstract: The present invention provides a method for fabricating a pixel cell of CMOS image sensor, comprising: preparing a semiconductor substrate divided into region I and region II; forming an insulation layer on the surface of the semiconductor substrate in the region I and a gate dielectric layer on the surface of the semiconductor substrate in the region II; forming a poly-silicon gate on the surface of the semiconductor substrate in the region II; forming a deep doped well in the region I through an ion implantation with high energy; performing an ion implantation with low energy in the region I and an ion implantation for lightly doped source/drain in the region II simultaneously; and forming source/drain regions in the semiconductor substrate in the region II.

Abstract: A method of fabricating a semiconductor device includes forming a first film on a processed film, patterning the first film into a pattern with smaller width and a space with larger width, forming a second film along upper and side surfaces of first film and an upper surface of second film, etching the second film thereby to expose upper surfaces of first film and processed film while part of second film remains along the side surface of first film, etching the first film under the condition that the first film has higher etch selectivity than the second film, etching an upper part of second film under the condition that the second film has a higher etch selectivity than the processed film, after the first film has been etched, and etching the processed film with the second film serving as mask after the upper part of second film has been etched.

Abstract: An impurity-activating thermal process is performed after a target is subjected to an impurity introduction step. In this thermal process, while a spike RTA process including a holding period for holding a temperature at a predetermined temperature is performed, at least one iteration of millisecond annealing at a temperature higher than the predetermined temperature is performed during the holding period of the spike RTA process.

Abstract: Packaging is substantially entirely removed from an integrated circuit die. The method allows the batch processing of several integrated circuit dies, such that packaging is removed from each die approximately simultaneously.

Abstract: To provide a manufacturing method of a semiconductor device using an SOI substrate, by which mobility can be improved. A plurality of semiconductor films formed using a plurality of bond substrates (semiconductor substrates) are bonded to one base substrate (support substrate). At least one of the plurality of bond substrates has a crystal plane orientation different from that of the other bond substrates. Accordingly, at least one of the plurality of semiconductor films formed over one base substrate has a crystal plane orientation different from that of the other semiconductor films. The crystal plane orientation of the semiconductor film is determined in accordance with the polarity of a semiconductor element formed using the semiconductor film. For example, an n-channel element in which electrons are majority carriers is formed using a semiconductor film having a face {100}, and a p-channel element in which holes are majority carriers is formed using a semiconductor film having a face {110}.

Abstract: An embodiment of a method for manufacturing an optical ring resonator device is disclosed. The method forms a ring resonator waveguide on a semiconductor substrate, forms an unoriented electro-optic polymer cladding over the ring resonator waveguide, and forms electrodes on the semiconductor substrate. The unoriented electro-optic polymer cladding is configured to change orientation under an applied electric field, and the electrodes are coupled to the optical ring resonator for manipulation of the electric field applied to the oriented electro-optic polymer cladding for rapid voltage tuning of its index.

Abstract: A system in package (10) has a, preferably wireless, test controller (20) for testing each die (30) after it has been mounted onto the substrate of the system in package (10), and a faulty die (30) is repaired before a next die (30) is mounted onto the substrate (15). This way, the system in package (10) can be tested during the intermediate stages of its manufacturing, thus ensuring that all dies (30) function correctly before sealing the dies in the single package. Consequently, a method for manufacturing a system in package (10) is obtained that has an improved yield compared to known manufacturing methods.

Abstract: Improved probing of closely spaced contact pads is provided by an array of vertical probes having all of the probe tips aligned along a single contact line, while the probe bases are arranged in an array having two or more rows parallel to the contact line. With this arrangement of probes, the probe base thickness can be made greater than the contact pad spacing along the contact line, thereby advantageously increasing the lateral stiffness of the probes. The probe tip thickness is less than the contact pad spacing, so probes suitable for practicing the invention have a wide base section and a narrow tip section.

Abstract: A method of preparing a floating trap type device on a substrate is described. The method comprises forming a trap layer structure on a substrate, and modifying a composition of one or more layers in the trap layer structure by exposing the trap layer structure to a gas cluster ion beam (GCIB).

Abstract: A non-volatile memory cell and the fabrication method thereof are provided. The non-volatile memory cell comprises a top electrode, a bottom electrode and an oxide layer disposed between the top electrode and the bottom electrode. The oxide layer comprises a relatively low oxygen content layer adjacent to the bottom electrode, a relatively high oxygen content layer adjacent to the top electrode, and a transition layer disposed between the relatively high and the relatively low oxygen content layers. The transition layer has an oxygen concentration within a range between those of the relatively high and the relatively low oxygen content layers.

Abstract: Method for metallization of at least one photovoltaic cell comprising a substrate based on a semiconductor with a first type of conductivity, a layer doped with a second type of conductivity produced in the substrate and forming a front face of the substrate, an antireflection layer produced on the front face of the substrate and forming a front face of the photovoltaic cell. The method comprises at least the steps of: a) producing at least one metallization on the front face of the photovoltaic cell, b) a first annealing of the photovoltaic cell at a temperature between around 800° C. and 900° C., c) producing at least one metallization on the rear face of the substrate, d) a second annealing of the photovoltaic cell at a temperature between around 700° C. and 800° C.

Abstract: A method in which an oxide layer is formed on material defining and surrounding an emitter window. The technique comprises depositing a non-conformal oxide layer on the surrounding material and in the emitter window, whereby the thickness of at least a portion of the oxide layer in the emitter window is smaller than the thickness of the oxide layer on the surrounding material outside the emitter window; and removing at least a portion of the oxide layer in the emitter window so as to reveal at least a portion of the bottom of the emitter window whilst permitting at least a portion of the oxide layer to remain on the surrounding material. The technique can be used in the manufacture of a self-aligned epitaxial base BJT (bipolar junction transistor) or SiGe HBT (hetero junction bipolar transistor).

Abstract: A method for manufacturing a sensor image may include forming a pixel array including a photodiode structure and an insulating film structure in an active area of a semiconductor substrate; forming a metal pad on the insulating film structure; forming a dielectric and/or etch stop film on the metal pad (and optionally over the pixel array); forming a protective layer on the dielectric and/or etch stop film; and forming a pad opening and a pixel opening by etching the protective layer.

Abstract: Method for annealing at least one photovoltaic cell comprising a substrate based on silicon with a first type of conductivity, a layer doped with a second type of conductivity produced in the substrate and forming a front face of the substrate, an antireflection layer produced on the front face of the substrate and forming a front face of the photovoltaic cell, at least one metallization on the front face of the cell and at least on metallization on a rear face of the substrate. This method comprises at least the steps of: a) a first annealing of the photovoltaic cell at a temperature between around 700° C. and 900° C., b) a second annealing of the photovoltaic cell at a temperature between around 200° C. and 500° C., at ambient pressure and in ambient air, with hydrogen being diffused in the substrate during the process.

Abstract: A method of manufacturing semiconductor devices comprises forming an semiconductor layer of the first conduction type on a substrate of the first conduction type; forming an anti-oxidizing layer on the surface of the semiconductor layer of the first conduction type, the anti-oxidizing layer having an aperture only through a region for use in formation of a guard ring layer of the second conduction type; forming the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type through implantation of ions into a surface where said anti-oxidizing layer is formed; forming an oxide layer at least in the aperture; forming a base layer of the second conduction type adjacent to the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type; and forming a diffused layer of the first conduction type through implantation of ions into the base layer of the second conduction type.

Abstract: A uniform layer of non-conductive material, e.g., epoxy, is screen printed onto the backside of an integrated circuit wafer to a required thickness, and then heated until it is hard cured (C-stage). The integrated circuit wafer having the hard cured coating is then sawn apart to separate the individual integrated circuit dice. A non-conductive adhesive is dispensed onto mating faces of die attach paddles of leadframes. The dice are placed into the non-conductive adhesive and then the die and die attach paddle assembly are heated to hard cure the adhesive between the mating faces of the die and die attach paddle. This provides long term electrical isolation of the integrated circuit die from the die attach paddle, and effectively eliminates silver migration from the die attach paddle which causes conductive paths to form that increase unwanted leakage currents in the die and ultimately cause failure during operation thereof.