Patents Examined by Kaushikkumar M Patel
  • Patent number: 11604732
    Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device perform operations comprising receiving a sequence of read commands from a memory sub-system controller; retrieving first data by executing a first read command of the set of read commands; storing the first data in a first portion of a cache of the memory device; responsive to determining that the memory device is in a suspended state, determining whether a first address range specified by the first read command overlaps with a second address range specified by a second read command of the set of read commands; responsive to determining that the first address range does not overlap with the second address range, retrieving second data by executing the second read command and storing the second data in a second portion of the cache; transferring the first and second data to the controller.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Sundararajan N. Sankaranarayanan, Eric Lee
  • Patent number: 11593011
    Abstract: Techniques manage spare extents based on a dynamic window. In particular, in response to determining that the number of spare extents in a source storage device of a plurality of storage devices is lower than a predetermined threshold, a source extent is selected from the source storage device, and the source extent is an extent in a created stripe included in a storage system. Based on a set of extents other than the source extent in the stripe, a set of storage device sequences respectively associated with the set of extents are determined. A destination extent is identified from a plurality of spare extents in the set of storage device sequences. Data in the source extent is migrated to the destination extent. Accordingly, load balancing of the spare extents in each storage device of the storage system may be ensured.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: February 28, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Chi Chen, Huijuan Fan
  • Patent number: 11586562
    Abstract: A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 21, 2023
    Assignee: Marvell Asia PTE, LTD.
    Inventors: Enrique Musoll, Tsahi Daniel
  • Patent number: 11579777
    Abstract: In a method disclosed for writing data, a device receives data, divides the data into one or more data fragments, obtains a first parity fragment based on the one or more data fragments and a second parity fragment of a written data fragment in a stripe distributed across a plurality of nodes, stores the one or more data fragments and the first parity fragment in the stripe.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 14, 2023
    Inventors: Siwei Luo, Lei Zhang, Feng Wang, Xin Fang
  • Patent number: 11573862
    Abstract: Systems and methods for performing application aware backups and/or generating other application aware secondary copies of virtual machines are described. For example, the systems and methods described herein may access a virtual machine, automatically discover various databases and/or applications (e.g., SQL, Exchange, Sharepoint, Oracle, and so on) running on the virtual machine, and perform data storage operations that generate a backup, or other secondary copy, of the virtual machine, as well as backups, or other secondary copies, of each of the discovered applications.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: February 7, 2023
    Assignee: Commvault Systems, Inc.
    Inventors: Sudha Krishnan Iyer, Rahul S. Pawar
  • Patent number: 11561867
    Abstract: Techniques disclosed herein provide techniques for coordinating host devices to synchronize data copy operations on storage arrays in an active-active storage configuration. For example, a method comprises managing generation of a backup copy of data in each of a set of storage arrays in an active-active storage configuration by causing one or more host devices that access the set of storage arrays to synchronously halt input-output operations associated with the set of storage arrays prior to causing the backup copy to be created in each of the set of storage arrays.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: January 24, 2023
    Assignee: EMC IP Holding Company LLC
    Inventor: Sunil Kumar
  • Patent number: 11556476
    Abstract: A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: January 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mu-Tien Chang, Krishna T. Malladi, Dimin Niu, Hongzhong Zheng
  • Patent number: 11550720
    Abstract: Entries in a cluster-to-caching agent map table of a data processing network identify one or more caching agents in a caching agent cluster. A snoop filter cache stores coherency information that includes coherency status information and a presence vector, where a bit position in the presence vector is associated with a caching agent cluster in the cluster-to-caching agent map table. In response to a data request, a presence vector in the snoop filter cache is accessed to identify a caching agent cluster and the map table is accessed to identify target caching agents for snoop messages. In order to reduce message traffic, snoop message are sent only to the identified targets.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: January 10, 2023
    Assignee: Arm Limited
    Inventors: Gurunath Ramagiri, Jamshed Jalal, Mark David Werkheiser, Tushar P Ringe, Mukesh Patel, Sakshi Verma
  • Patent number: 11544193
    Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: January 3, 2023
    Assignee: Apple Inc.
    Inventors: James Vash, Gaurav Garg, Brian P. Lilly, Ramesh B. Gunna, Steven R. Hutsell, Lital Levy-Rubin, Per H. Hammarlund, Harshavardhan Kaushikkar
  • Patent number: 11537309
    Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: December 27, 2022
    Assignee: Texas Instmments Incorporated
    Inventors: Puneet Sabbarwal, Indu Prathapan
  • Patent number: 11537311
    Abstract: Various examples herein described are directed to methods, apparatuses and computer program products configured for dynamically replicating and/or converting source data objects in one or more external-access-limited source data object repositories to replica data objects in one or more external-service-accessible replica data object repositories in a network service cloud. For example, a network service server of the network service cloud may generate a plurality of bootstrap task objects and at least one change data capture (CDC) task object, and may generate the replica data objects based on the task objects.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: December 27, 2022
    Inventors: Rohan Dhupelia, Stephen Lee, Carlos Khatchikian, Jon Hartlaub, Arie Friedman, Benjamin Jackson
  • Patent number: 11537294
    Abstract: A position-measuring device includes a graduation carrier having a measuring graduation, position measurement electronics, a data memory and a power supply. The data memory includes a first memory which is a volatile memory for storing additional data, a second memory which is a writable non-volatile memory, and a memory controller for controlling transfer and storage of additional data from the first into the second memory. The power supply includes an input stage, a first output stage for the position measurement electronics, a second output stage for the data memory, and a voltage monitor which will turn off the first output stage of the power supply in response to a drop below a minimum value and signal the drop to the memory controller by a backup signal. In response to the backup signal, the memory controller will transfer additional data from the first memory into the second memory.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: December 27, 2022
    Inventor: Elmar Mayer
  • Patent number: 11531620
    Abstract: A data processing network includes request nodes with local memories accessible as a distributed virtual memory (DVM) and coupled by an interconnect fabric. Multiple DVM domains are assigned, each containing a DVM node for handling DVM operation requests from request nodes in the domain. On receipt of a request, a DVM node sends a snoop message to other request nodes in its domain and sends a snoop message to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes, and send a completion message to the first request node. Each peer DVM node sends snoop messages to the request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this way, DVM operations are performed in parallel.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: December 20, 2022
    Assignee: Arm Limited
    Inventors: Kishore Kumar Jagadeesha, Jamshed Jalal, Tushar P Ringe, Mark David Werkheiser, Premkishore Shivakumar, Lauren Elise Guckert
  • Patent number: 11531604
    Abstract: Methods, computer program products, computer systems, and the like are disclosed that provide for scalable deduplication in an efficient and effective manner. For example, such methods, computer program products, and computer systems can include determining whether a source data store and a replicated data store are unsynchronized and, in response to a determination that the source data store and the replicated data store are unsynchronized, performing a resynchronization operation. The source data stored in the source data store is replicated to replicated data in the replicated data store. The resynchronization operation resynchronizes the source data and the replicated data.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: December 20, 2022
    Assignee: Veritas Technologies LLC
    Inventors: Rushikesh Patil, Sunil Hasbe
  • Patent number: 11520700
    Abstract: A holistic view of cache class of service (CLOS) to include an allocation of processor cache resources to a plurality of CLOS. The allocation of processor cache resources to include allocation of cache ways for an n-way set of associative cache. Examples include monitoring usage of the plurality of CLOS to determine processor cache resource usage and to report the processor cache resource usage.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: Malini K. Bhandaru, Iosif Gasparakis, Sunku Ranganath, Liyong Qiao, Rui Zang, Dakshina Ilangovan, Shaohe Feng, Edwin Verplanke, Priya Autee, Lin A. Yang
  • Patent number: 11513728
    Abstract: A storage device includes a main storage and a storage controller to control the main storage. The main storage stores data and includes a plurality of nonvolatile memory devices. The storage controller loads at least one of (a) at least a portion of mapping tables and (b) at least one of a portion of directories to a host memory buffer included in an external host device, based on at least one of a size of the host memory buffer and locality information associated with a data access pattern of the host device. The mapping tables are stored in the nonvolatile memory devices and the mapping tables indicate a mapping relationship between a physical address and a logical address of corresponding ones of the nonvolatile memory devices. The directories store address information of the mapping tables.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: November 29, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su-Ryun Lee, Bum-Hee Lee
  • Patent number: 11494305
    Abstract: A linked list searching method and device are configured to search a linked list by using a cache memory. The method includes the operations of: writing the linked list in a memory; writing the data of a first node in a first row of a tag memory of the cache memory, and writing an address of the first node in a first row of a data memory of the cache memory; writing the data of a second node in a second row of the tag memory, and writing the address of the second node in a second row of the data memory; and searching the data of the second node in the tag memory to directly retrieve the address of the second node when searching the address of the second node in the linked list according to the data of the second node.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 8, 2022
    Inventor: Yen-Ju Lu
  • Patent number: 11487664
    Abstract: A technique performs data reduction on host data of a write request during ingest under certain circumstances. Therein, raw host data of a write request is placed from the host into a data cache. Further, a data reducing ingest operation is performed that reduces the raw host data from the data cache into reduced host data (e.g., via deduplication, compression, combinations thereof, etc.). After completion of the data reducing ingest operation, a late-binding operation is performed that updates a mapper with ability to access the reduced host data from secondary storage. Such ingest-time data reduction may be enabled/disabled (e.g., turned on or off) per input/output (I/O) operation (e.g., used only for relatively large asynchronous I/O operations) and/or activated in situations in which the ingest bandwidth is becoming a bottleneck.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 1, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Vamsi K. Vankamamidi, Ronen Gazit
  • Patent number: 11487653
    Abstract: Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Qing Liang
  • Patent number: 11467963
    Abstract: A method, computer program product, and computing system for receiving, at a node of a multi-node storage system, one or more updates to a reference count associated with a metadata block. One or more reference count deltas associated with the metadata block may be stored in a cache memory system of the node. An existing copy of the metadata block in a cache memory system of each other node of the multi-node storage system may be retained.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: October 11, 2022
    Inventors: Bar David, Bar Harel, Dror Zalstein