Patents Examined by Kavid E. Graybill
  • Patent number: 5643830
    Abstract: A technique for improving power distribution to an semiconductor die while simultaneously reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by providing the signal-carrying bond pads in a collinear arrangement along an axis of the die, and providing power-carrying bond pads in an off-axis location. The on-axis configuration of signal-carrying bond pads minimizes lateral thermal displacements of the bond pads relative to the axis, which minimizes any longitudinal, compressive end displacements of leadframe fingers or bond wires, thereby minimizing thermally induced mechanical stresses of the bond pad interfaces to the die. The positioning of the power-carrying bond pads off-axis reduces the length of internal (to the die) wiring required to connect circuitry on the die to the power-carrying bond pads.
    Type: Grant
    Filed: January 23, 1995
    Date of Patent: July 1, 1997
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta