Patents Examined by Kee Tung
  • Patent number: 9170421
    Abstract: This disclosure provides systems, methods and apparatus for providing multi-level multi-state shutter assemblies. The shutter assembly includes at least a first shutter at a first height over a substrate and a second shutter at a second height over the substrate. Both the first shutter and the second shutter can be operated in an open or closed state for passing or partially blocking light propagating through an aperture. In some implementations, the shutter assembly can operate in four states: a fully transmissive state, a fully obstructive state and two partially transmissive states based on the open or closed states of the first and second shutters.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: October 27, 2015
    Assignee: Pixtronix, Inc.
    Inventors: Jianru Shi, Richard S. Payne, Timothy J. Brosnihan, Eugene Fike, Edward Buckley, Javier Villarreal
  • Patent number: 9165490
    Abstract: A 3D/2D multi-primary color image device is provided with an optical unit to direct a first image to a first group of viewers and a second image to a second group of viewers. Each color dot of the multi-primary color image device comprises at least two color sections controlled independently. A first group of viewers and a second group of viewers can view simultaneously and respectively a first image and a second image.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: October 20, 2015
    Assignee: VP ASSETS LIMITED
    Inventors: Gia Chuong Phan, Hon Wah Wong
  • Patent number: 8643669
    Abstract: A measurement and testing system includes a measurement assembly having at least one measurement device, at least one visual display device, and a data acquisition and processing device operatively coupled to the at least one measurement device of the measurement assembly and the visual display device. In one embodiment, the data acquisition and processing device is further configured to generate a timeline bar with date icons on the output screen of the visual display device. In other embodiments, the data acquisition and processing device is further configured to automatically displace a side bar menu on the output screen when a user switches from a current mode to another mode, read external files containing one or more testing routines written off-site, and/or automatically alert a system user when one or more signals from a measurement device are no longer detected and/or are corrupted.
    Type: Grant
    Filed: December 22, 2012
    Date of Patent: February 4, 2014
    Assignee: Bertec Corporation
    Inventors: Todd Christopher Wilson, Necip Berme
  • Patent number: 7436410
    Abstract: A system for configuring a chip to perform certain operations is provided. The system includes a CPU. The CPU is in communication with a graphics controller. The graphics controller includes a non-volatile memory for storing a look up table (LUT). The graphics controller further includes a register port. The CPU provides a LUT value to the register port. Look up circuitry, which is in communication with the LUT register port, receives the LUT value from the register port and the LUT circuitry retrieves a corresponding LUT sequence from the LUT. The LUT sequence represents an operation to be performed by the LUT circuitry. The system is further provided with a register block, which can be programmed with values based on the operation to be performed.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: October 14, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Phil Van Dyke, Barinder Singh Rai
  • Patent number: 7397477
    Abstract: A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory locations. Memory addresses are decoded to access the addressable memory locations of a first block of memory in accordance with a first memory address allocation format and the memory addresses are decoded to access the addressable memory locations of a second block of memory in accordance with a second memory address allocation method different from the first memory address allocation format.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: July 8, 2008
    Assignee: Micron Technology, Inc.
    Inventor: William Radke
  • Patent number: 7391419
    Abstract: An information distribution system configured to deliver various types of content provided by an information distributor to information receivers through a network and transmitting the content to be distributed converted to colors, color values, or color digital values. By converting the content to colors, color values, or color digital values, it is possible to reduce the amount of information transmitted. Due to this, it becomes possible to shorten the time required for distribution of content and to improve practicality. Further, it becomes possible to reduce the distribution costs.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: June 24, 2008
    Assignee: Tani Electronics Corporation
    Inventor: Okie Tani
  • Patent number: 7388988
    Abstract: In one embodiment, the present invention is directed to a method for processing boundary information of a graphical object. The method may comprise: receiving a graphical image that comprises the graphical object, wherein the graphical object is defined by at least the boundary information; determining a plurality of vertices from the boundary information; and creating an approximated boundary utilizing at least the plurality of vertices, the graphical image, and a predetermined function that is operable to detect a contour between a pair of vertices by analyzing the graphical image.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: June 17, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Huitao Luo
  • Patent number: 7202872
    Abstract: One embodiment of the present invention is directed to a graphics system comprising logic for generating a mask that identifies bits within a plurality of bits that are not to be impacted by a subsequent computation. The graphics system further comprises compression logic that is responsive to the mask for generating a compressed bit stream, such that the bits that are not to be impacted by the computation are not included in the compressed bit stream. Another embodiment of the present invention is directed to a graphics system comprising logic for generating a mask identifying positions within a plurality of positions of a bit stream that are to be removed during a compression operation.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: April 10, 2007
    Assignee: VIA Technologies, Inc.
    Inventors: Timour Paltashev, Boris Prokopenko
  • Patent number: 6677953
    Abstract: A system and method are provided for a dedicated hardware-implemented viewport operation in a graphics pipeline. Included is a transform/lighting module for transforming and lighting vertex data. Also provided is viewport hardware coupled to the transform/lighting module for performing a viewport operation on the vertex data. A rasterizer is coupled to the viewport hardware for rendering the vertex data.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: January 13, 2004
    Assignee: NVIDIA Corporation
    Inventors: Kirk E. Twardowski, Gary Tarolli